Stop Clock State Machine; Extended Halt Maximum Power - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Features
Table 7-2.

Extended HALT Maximum Power

Symbol
P
EXTENDED_HALT
Quad-Core Intel®
Xeon® Processor
E5300 Series
P
EXTENDED_HALT
Core Intel® Xeon®
Processor X5300
Series
Notes:
1. The specification is at T
VID while running in HALT state.
2. This specification is characterized by design.
3. Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the
HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage
operating point. Values represent SKUs with Extended HALT state (30 W) and without Extended HALT state
(34 W).
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus to core frequency ratio back to the original value.
Figure 7-1.

Stop Clock State Machine

Normal State
Normal execution
STPCLK#
Asserted
Stop Grant State
BCLK running
Snoops and interrupts allowed
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Parameter
Extended HALT
State Power
Quad- Extended HALT
State Power
= 50°C and nominal V
CASE
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
STPCLK#
De-asserted
Min Typ
. The VID setting represents the maximum expected
CC
Snoop Event Occurs
Snoop Event Serviced
Max Unit Notes
30/34 W 1,2,3
50 W 1,2
Extended HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoop Snoop
Event Event
Occurs Serviced
Extended HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant Snoop State
BCLK running
Service snoops to caches
93