Front Side Bus Frequency Select Signals (Bsel[2:0]); Core Frequency To Fsb Multiplier Configuration; Bsel[2:0] Frequency Table - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Table 2-1.

Core Frequency to FSB Multiplier Configuration

Core Frequency to FSB
Multiplier
Notes:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series
Specification Update.
4. The lowest bus ratio supported is 1/6.
2.4.1

Front Side Bus Frequency Select Signals (BSEL[2:0])

Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to V
to select the FSB frequency. Please refer to
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
Table 2-2.

BSEL[2:0] Frequency Table

BSEL2
18
Core Frequency with
333.333 MHz Bus Clock
1/6 2 GHz
1/7 2.33 GHz
1/8 2.66 GHz
1/9 3 GHz
BSEL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Core Frequency with
266.666 MHz Bus Clock
1.60 GHz
1.86 GHz
2.13 GHz
2.40 GHz
Table 2-15 for DC specifications.
BSEL0 Bus Clock Frequency
0
1
0
1
0
1
0
1
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
Notes
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
, and are used
TT
Table 2-2
266.666 MHz
Reserved
Reserved
Reserved
333.333 MHz
Reserved
Reserved
Reserved