Table 4.10 Bit Definitions Of Atapi Features Register; Table 4.11 Bit Definitions Of Atapi Interrupt Reason Register - Fujitsu MCM3064AP Product Manual

Host Interface
4.3.1.9 ATA Features register
This register is used for the SET FEATURES command.
4.3.1.10 ATAPI Features register
This register's bits are defined as shown below.

Table 4.10 Bit definitions of ATAPI Features register

7 6
All values in bits 7 to 2 are ignored.
OVERLAP is not used. The ODD ignores the value set in this bit.
When DMA is 1, the ODD performs DMA transfer for data transfer.
4.3.1.11 ATA Sector Count register
This register is used for the SET FEATURES command.
4.3.1.12 ATAPI Interrupt Reason register
This register's bits are defined as shown below.

Table 4.11 Bit definitions of ATAPI Interrupt Reason register

7 6
Reserved Reserved Reserved
(0b) (0b)
When RELEASE is 1, the ODD releases the ATA bus before a command
being executed is completed.
I/O indicates the direction of data transfer. See Table 4.12.
C/D indicates the type of transfer. See Table 4.12.
4-10
5 4
Reserved
5 4
Reserved Reserved
(0b) (0b) (0b)
3 2
OVERLAP
3 2
RELEASE
1 0
DMA Write
1 0
I/O C/D
C156-E227-01EN
Read