Signal Description; Table 4.2 Signal Description - Fujitsu MCM3064AP Product Manual

Host Interface

4.2 Signal Description

PIN Signal name
1 RESET-
3, 5, 7, 9, 11, DD7-0
13, 15, 17, 18, DD15-8
16, 14, 12, 10,
8, 6, 4
21 DMARQ
23 DIOW-
STOP
25 DIOR-
HDMARDY-
HSTROBE
27 IORDY
DDMARDY-
DSTROBE
28 CSEL
29 DMACK-
31 INTRQ
32 IOCS16-
36, 33, 35 DA2, 1, 0
34 PDIAG-
4-4

Table 4.2 Signal description (1/2)

I/O
I Reset signal
I/O The low-order bus is a 8-bit bidirectional bus signal for
exchanging the status, data, and control data between
the host and ODD.
The high-order bus is used for 16-bit data transfers only.
O Data request signal for DMA transfer
I Write strobe signal.
Indicates that transfer has ended at Ultra DMA transfer.
I Read strobe signal
Indicates that the host can receive Ultra DMA data at
Ultra DMA in transfer.
The ODD latches data at both edges of this signal at
Ultra data out transfer.
O This is the ready signal for the host computer. The ODD
uses this signal to request an extension of the transfer
cycle when it cannot prepare a response to a data
transfer request from the host computer in time.
Indicates that the ODD can receive Ultra DMA data at
Ultra DMA out transfer.
The host latches data at both edges of this signal at Ultra
data in transfer.
I Sets the ODD to the master (device 0) or slave (device
1).
Effective by jumpering.
I Answer signal in response to DMARQ during DMA
transfer
O Interrupt signal to the host
O Indicates that the ODD is ready for 16-bit transfer when
the host addresses the 16-bit data port during PIO
transfer.
O Address signal used by the host to address the ODD task
file register
I/O Used by the slave (device 1) to notify the master (device
0) that diagnostics ended
Description
C156-E227-01EN