I/O Sub-System; Pci Subsystem; Table 10. Pci Bus Segment Characteristics - Intel SE7525GP2 Technical Manual

Functional Architecture
requires that the spare DIMM be at least the size of the largest primary DIMM in use.) The MCH
will also begin tracking the progress of its built-in memory scrub engine. Once the scrub engine
has covered every location in the primary DIMM, the duplicate write function will have copied
every data location to the spare. At that point, the MCH can switch the spare into primary use,
and take the failing DIMM off-line.
This mechanism requires no software support once it has been programmed and enabled, until
the threshold detection has been triggered to request a data copy. Hardware will detect the
threshold initiating fail-over, and escalate the occurrence of that event as directed (signal an
SMI, generate an interrupt, or wait to be discovered via polling). Whatever software routine
responds to the threshold detection must select a victim DIMM (in case multiple DIMMs have
crossed the threshold prior to sparing invocation) and initiate the memory copy. Hardware will
automatically isolate the "failed" DIMM once the copy has completed. The data copy is
accomplished by address aliasing within the DDR control interface, thus it does not require
reprogramming of the DRAM row boundary (DRB) registers, nor does it require notification to
the operating system that anything has occurred in memory.
3.6

I/O Sub-System

The I/O sub-system is made up of several components: the MCH providing the PCI Express*
interface and the Intel
controller, Super I/O chip, and Management Sub-system. This section describes the function of
each I/O interface and how they operate on these server boards.
3.6.1

PCI Subsystem

The primary I/O interface is PCI, with two independent PCI bus segments. A PCI 33 MHz, 32-bit
bus segment (P32-A) with two connectors and a PCI-X 64-bit / 66 MHz segment (P64-A) are
controlled through the Intel
Express4) bus segment controlled from the MCH on the Intel Server Board SE7320SP2 is
available. Or one x4 PCI Express bus segment and one x16 PCI Express bus segment (P64-
Express16) are available on the Intel Server Board SE7525GP2. The table below lists the
characteristics of the different PCI bus segments.
PCI Bus Segment
P32-A
P64-A
P64-Express4
P64-Express16
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem
All 32-bit, 33-MHz PCI I/O is directed through the Intel
33-MHz PCI segment created by the Intel 6300ESB I/O controller is known as the P32-A
segment. The P32-A segment supports the following devices:
2D/3D Graphics Accelerator: ATI* Rage XL video controller
30
®
6300ESB I/O controller providing the interface for the onboard video
®
6300ESB I/O controller. Additionally, one x4 PCI Express* (P64-

Table 10. PCI Bus Segment Characteristics

Voltage Width
5 V 32-bits 33 MHz
3.3 V 64-bits 66 MHz
1.6 V 64-bits x4
1.6 V 64-bits x16
Intel® Server Boards SE7320SP2 and SE7525GP2
Speed Type
PCI 2 slots
PCI-X 2 slots
PCI-E 1 slot
PCI-E 1 slot (SE7525GP2 only)
®
6300ESB I/O controller. The 32-bit,
PCI I/O Card Slots
Revision 4.0