Timeout Fault Detection; Summary Of Timeout Conditions - HP 7925D Service Manual

7925
1-51. Illegal Cylinder Address Detection. The in-
ternal control bus bits DO through D9 are continually
monitored by the illegal cylinder address detector on servo
PCA-A3. If a cylinder address greater than 822 is de-
tected, the ICA signal will become active (lCA
=
1). This
will inhibit the illegal cylinder address from being clocked
into the new cylinder address register (see figure 4-29).
The seek check flip-flop will be clocked set on the leading
edge of the decoded SEEK command. The seek check flip-
flop is reset by NDPS whenever the power-on sequence is
initiated (lLF
=
1), the RUN/STOP switch is set to RUN
(RUN
=
1), or a CPS command is decoded (CPS
=
1). In
addition, the seek check flip-flop is reset by CYL whenever
the seek home command is active (SKH
=
0) or a seek to a
legal cylinder address command is decoded. Further, if the
heads are in motion (ACRY
=
1) when the SEEK com-
mand is decoded, the seek check flip-flop will be clocked
set on the leading edge of the decoded SEEK command.
This will notify the controller that the disc drive is in the
process of executing a previous SEEK command.
1-52. Illegal Head Address Detection. The inter-
nal control bus bits D8, D9, DI0, and Dll are continually
monitored by the illegal head address detection circuitry
on I/O sector PCA-A2. If a head address greater than 8 is
detected, the illegal head address flip-flop will be clocked
set on the leading edge of the decoded ADR command. In
addition, the illegal head address will not be clocked into
the head address register (see figure 4-28). The illegal
head address flip-flop is reset by NDPS whenever the
power-on sequence is initiated (lLF
=
1), the RUN/STOP
switch is set to RUN (RUN
=
1), or a CPS command is
decoded (CPS
=
1).
1-53. Illegal Sector Address Detection. The inter-
nal control bus bits DO and D7 are continually monitored
by the illegal sector address detection circuitry on I/O
sector PCA-A2. If a sector address greater than 63 is
Theory of Operation
detected, the illegal sector address flip-flop will be clocked
set on the leading edge of the decoded ADR or XMS com-
mand. In addition, the illegal sector address will not be
clocked into the sector address register (see figure 4-27).
The illegal sector address flip-flop is reset by NDPS
whenever the power-on sequence is initiated (lLF
=
1),
the RUN/STOP switch is set to RUN (RUN = 1), or a CPS
command is decoded (CPS = 1).
1-54. TIMEOUT FAULT DETECTION. Each
time a forward or reverse seek operation is commanded,
circuits on drive control PCA-A4 initiate a 120 milli-
second time-out cycle. When the SEEK command is de-
coded (SK
=
1), the timeout cycle flip-flop is set to initiate
the 120 millisecond timout cycle. A 135 Hz signal (TCC)
derived from the spindle speed (see figure 4-29) is used to
clock the timeout counter. Similarly, a 1667 millisecond
timout cycle is initiated each time an initial head load,
normal head unload, or recalibrate operation is com-
manded. Table 1-5 provides a summary of those condi-
tions that initiate and those conditions that cancel a
timeout cycle. If the event being timed is not cancelled
before the timeout counter times out, a timeout fault will
be declared. When a timeout fault is detected, the follow-
ing events will occur:
• TOFL signal becomes active (TOFL
=
0).
• T fault LED lights (TOFL
=
0).
• Timeout counter reset is inhibited (TOFL
=
0).
• Heads are unloaded, spindle is braked to a stop, and the
pack chamber door is unlatched. Refer to table 1-6 for
the specific events.
The timeout counter is reset by DPS whenever the power-
on sequence is initiated (lLF
=
1)
or the RUN/STOP
switch is set to RUN (RUN
=
1).
Table 1-5. Summary of Timeout Conditions
TIMEOUT
INITIATING CONDITION
CYCLE
CANCELLING CONDITION
120 ms
Seek command (SK
=
1)
Heads settled on specified cylinder within 120 milliseconds
(TOFl • ACRY
=
1).
1667 ms
Initial Head load (SKH
=
0)
Heads settled on cylinder 0 within 1667 milliseconds
(TOFl • ACRY
=
1).
1667 ms
Normal head unload
Heads reach fully retracted position within 1667 milliseconds
(RET. TOFl
+
IlFl
=
1)
(TOFl • RET. CRB
=
1).
1667 ms Recalibrate command
Heads are settled on cylinder 0 within 1667 milliseconds
(RH
=
1) (TOFl • 2 ACRY
=
1).
1-27