HP 7925D Service Manual page 202

7925
summing junction also receives a voltage which is propor-
tional to the linear velocity of the carriage. This voltage is
developed by the velocity transducer and shaft and is fed
back through the tachometer buffer and FET switch.
The summing amplifier compares the buffered output
from the tachometer (measured velocity) with the output
from the velocity curve generator (velocity command) and
produces a current command which drives the difference
to zero. This current command can be observed at the test
point on servo PCA-A3 labeled "CC". The amount of cur-
rent available may be limited by the current command
limiter. This circuit is activated by the seek inhibit signal
(SKI
=
1).
The current command is coupled through the voltage gain
amplifier to the linear motor power amplifier via a closed
FET switch. Both of these amplifiers are located on PMR
PCA-A9. The FET switch and linear motor relay were
both activated when the head positioning servo loop was
enabled (SEN
=
1) during the initial head load operation.
Power is applied to the linear coil through the energized
linear motor relay. The linear motor voltage developed
can be observed at the test point labeled ~'LMV" and a
sample of linear motor current can be observed at the test
point labeled "LMC". Both of these test points are located
on PMR PCA-A9.
As the heads begin to move across the disc surfaces, the
ACRY signal will become inactive (ACRY = D. This will
cause future seek, recalibrate, or write operations to be
inhibited; and the attention reset flip-flop to be clocked
clear to reset the ACRY attention and retract attention
flip-flops (status bit 8
=
0).
In addition, the POS signal will be developed from the
servo code written on the servo surface. This signal can be
observed at the test point on track follower PCA-A5
(source) or servo PCA-A3 (destination) labeled
'~POS".
Every time the POS signal passes through zero volts, a
clock pulse is generated by the cylinder pulse generator on
servo PCA-A3. The first clock pulse is inhibited because
the first clock inhibit flip-flop was set when the seek com-
mand was decoded. This flip-flop will be clocked clear on
the leading edge of the TCD signal to enable subsequent
clock pulses to clock the present cylinder address counter.
The track center detector will produce the TCD signal
when the heads are within 1/4 track width of track center.
The state of the TCD signal can be observed at the test
point on servo PCA-A3 labeled ~~TCD".
The match logic monitors the digital difference applied to
the digital to analog converter. When the heads are
positioned within one cylinder from the addressed cylin-
der, the MATCH-l signal will become active
(MATCH-l = 0). This signal notifies the track center de-
tector that the present cylinder address count is one less
than the address stored in the new cylinder address regis-
ter. The last clock pulse is produced by the track center
detector rather than by the cylinder pulse generator. This
pulse is produced when the last one-quarter track of travel
Appendix A
is detected. When the present cylinder address count
equals the address stored in the new cylinder address
register, the MATCH signal will become active
(MATCH
=
D. The state of the MATCH-l and MATCH
signals can be observed at the test points on servo PCA-A3
labeled "Ml" and "M", respectively. When the MATCH
signal becomes active (MATCH
= D,
it disables the for-
ward or reverse velocity command to the summing junc-
tion of the summing amplifier, activates the fine position
FET switch, and increases the sensitivity of the track
center detector. With the fine position FET switch closed,
the current applied to the linear motor coil will be deter-
mined by the POS signal.
Once the track center of the addressed cylinder is detected
(TCD and FINE POSITION = 1), the SB signal will be-
come active (SB
=
0). This will inhibit tachometer feed-
back to the head positioning servo loop. After a 1.3 milli-
second delay to allow time for the heads to settle, the
ACRY signal will become active (ACRY
=
0). The drive
ready flip-flop is not affected. It remains set from the
initial head load operation.
When the ACRY signal becomes active (ACRY
=
0), it
cancels the 120 millisecond timeout cycle; causes the drive
busy status bit to be inactive (status bit 0 = 0); and clocks
the ACRY attention flip-flop set, which enables future
seek, recalibrate, or write operations. The state of the
ACRY signal can be observed at the test point on drive
control PCA-A4 labeled "ACRY".
The set output from the ACRY attention flip-flop causes
the attention status bit to be active (status bit 8
=
1). This
will notify the controller that the disc drive has completed
a seek operation to a legal cylinder. This status bit can be
selectively cleared by the controller if it issues a CLA
command.
The heads will remain settled over the addressed cylinder
until a set offset, recalibrate, or another seek command is
decoded, or until they are unloaded when the RUN/STOP
switch is set to STOP or a fault condition is detected.
A-47. OFFSET OPERATION. An offset operation
is used to move the heads in small increments to either
side of track center. This function is designed to permit
marginal data recovery. The controller issues a set offset
(SOF) command with the offset magnitude and sign on the
control bus. The internal control bus bits DO through D5
specify the offset magnitude in 63 increments of 12.5 mi-
croinches each, while bit D7 specifies the direction
(+
or
-) from track center. The disc drive decodes the command
and the SOF signal becomes active (SOF = 1) to clock the
offset magnitude and sign into the offset magnitude and
sign registers, respectively. Both of these registers are
located on track follower PCA-A5. They are both cleared
by the COF signal when the heads are initially loaded or
when a seek or recalibrate command is decoded. Therefore
if offset is desired, the offset magnitude and sign must be
re-specified after either of these operations is performed.
A·21