Summary Of Timeout Conditions - HP 7925D Service Manual

7925
A-58. TIMEOUT FAULT DETECTION. Each time
a forward or reverse seek operation is commanded, circuits
on drive control PCA-A4 initiate a 120 millisecond time-
out cycle. When the SEEK command is decoded (SK
=
1),
the timeout cycle flip-flop is set to initiate the 120 mil-
lisecond timeout cycle. A 135 Hz signal (TCC) derived
from the spindle speed (see figure A-21) is used to clock
the timeout counter. Similarly, a 1667 millisecond time-
out cycle is initiated each time an initial head load, nor-
mal head unload, or recalibrate operation is commanded.
Table A-5 provides a summary of those conditions that
initiate and those conditions that cancel a timeout cycle. If
the event being timed is not cancelled before the timeout
counter times out, a timeout fault will be declared. When a
timeout fault is detected, the following events will occur:
• TOFL signal becomes active (TOFL
=
0).
• T fault LED lights (TOFL
=
OJ.
• Timeout counter reset is inhibited (TOFL
=
0).
• Heads are unloaded, spindle is braked to a stop, and the
pack chamber door is unlatched. Refer to table A-6 for
the specific events.
The timeout counter is reset by DPS whenever the power-
on sequence is initiated (lLF
=
1) or the RUN/STOP
switch is set to RUN (RUN
=
1).
A-59. AGC FAULT DETECTION. The state of the
AGC signal is continually monitored by a circuit on servo
PCA-A3.
If
the servo AGe signal is lost while the heads
are located on or between cylinders 0 and 822, an AGC
fault will be declared. When an AGC fault is detected, the
following events will occur:
• AGC fault flip-flop is set (AGCF • DRDY
=
1).
• AGFL signal becomes active (AGFL
=
0).
• AGC fault
L~D
lights (AGFL
=
0),
Appendix A
• Heads are unloaded. Refer to table A-6, steps 1 through
8, for the specific events.
The AGC fault flip-flop is reset by NDPS whenever the
power-on sequence is initiated (lLF
=
1), the RUN/STOP
switch is set to RUN (RUN
=
1), or a CPS command is
decoded (CPS
=
1).
A-60. CARRIAGE BACK FAULT DETEC-
TION. The state of the CRB signal is continually moni-
tored by a circuit on drive control PCA-A4. If the CRB
signal becomes active (CRB
=
1) indicating that the heads
have been fully retracted, but the drive ready flip-flop has
not been reset by the RET signal (CRB and DRDY simul-
taneously active), a carriage back fault will be declared.
When a carriage back fault is detected, the following
events will occur:
• Carriage back fault flip-flop is set (CRB • DRDY
=
1).
• CBFL signal becomes active (CBFL
=
0).
• CB fault LED lights (CBFL
=
0).
• Heads are unloaded. Refer to table A-6, steps 1 through
8, for the specific events.
The carriage back fault flip-flop is reset by DPS whenever
the power-on sequence is initiated (lLF
=
1) or the RUN/
STOP switch is set to RUN (RUN
=
1).
A-61. INTERLOCK FAULT DETECTION. The
interlock fault detection circuitry on drive control PCA-A4
continually monitors the interlock chain, the -36, -24,
-12, +5, + 12, and +36 Vdc power supply voltages, the
temperature of the heat sink on PMR PCA-A9, and the
spindle fault logic on spindle logic PCA-A8. If anyone of
the PCA's (with the exception of indicator PCA-A11 and
fault indicator PCA-A12) is not firmly in place, the pack
chamber is disconnected, anyone of the monitored power
supplies falls below a specified value, the temperature of
Table A-5. Summary of Timeout Conditions
TIMEOUT
INITIATING CONDITION CANCELLING CONDITION
CYCLE
120 ms
Seek command (SK
=
1)
Heads settled on. specified cylinder within 120 milliseconds
(TOFl • ACRY
=
1).
1667 ms Initial Head load (SKH
=
0)
Heads settled on cylinder 0 within 1667 milliseconds
(TOFl • ACRY
=
1).
1667 ms Normal head unload
Heads reach fully retracted position within 1667 milliseconds
(RET. TOFl
+
IlFl
=
1)
(TOFl. RET. CRB
=
1).
1667 ms
Recalibrate command
Heads are settled on cylinder 0 within 1667 milliseconds
(RH
=
1)
(TOFl • 2 AeRY
=
1).
A-27