HP 7925D Service Manual page 206

7925
The appropriate head must be selected before a read or
write operation can be performed. The address of the de-
sired head is stored in the head address register on mi-
croprocessor PCA-A2. The head address register is ini-
tially cleared when NDPS becomes active (NDPS
=
0).
This occurs when power is first applied or when the
RUN/STOP switch is set to RUN. This will establish a
head address of zero which will remain in effect until the
contents of the head address register is changed by an
ADR command. Whenever an ADR command is issued by
the controller, a 4-bit head address is also supplied. Bits
DO, D1, D2, and D3 are checked to ensure that the address
is legal before it is stored in the head address register
(legal head addresses are 0 thru 8). An illegal head ad-
dress is not stored in the head address register, but instead
a seek check will result (status bit 3
=
1).
The stored head address is buffered by circuits on drive
control PCA-A4. The buffered head select bits (BRSO
through BRS3) are coupled to the input of the data head
decoder on RlW preamplifier PCA-A6. If no write faults
exist (WFLT
=
0), the center tap winding of the addressed
head will be switched to a
+
12 Vdc power source. The
multiple heads selected detector continuously monitors
the center tap windings, and if more than one head is
selected, a destructive MR fault will be declared.
A-53. READ MODE OPERATION. As the data
surfaces pass beneath the data heads, the magnetically
stored flux fields intersect the gap in the ferrite core. Gap
motion through the flux field causes a voltage to be in-
duced into the read/write winding wound around the core.
This induced voltage is analyzed by.the read circuitry to
define the data recorded on the data surface. Each flux
reversal (caused by a write current polarity change) gen-
erates a readback voltage pulse.
The read circuitry on RlW preamplifier PCA-A6 and drive
control PCA-A4 is always enabled in the read mode. A
differential signal is coupled from the selected head wind-
ings to the input of the preamplifier stage via the head
select diodes and the two conducting read/write mode FET
switches. The other heads and the write current paths are
isolated by back-biased diodes. The gain of the pre-
amplifier stage is set by the data AGC circuit on drive
control PCA-A4. The output of the preamplifier stage is
coupled through a balanced low-pass filter to the differen-
tiator stage. The differentiator stage transforms the read
data waveform such that the data points are represented
by zero crossings rather than the peaks produced at the
data head.
The differential .data from
RlW
preamplifier PCA-A6 is
coupled through a second balanced low-pass filter on drive
control PCA-A4 to the input of the fixed-gain read
amplifier. The output from this amplifier is coupled to the
zero crossing detector and data AGC circuit. The data
AGC circuit maintains a constant peak-to-peak level at
the input of the zero crossing detector by controlling the
gain of the preamplifier stage on R/W preamplifier
PCA-A6. The data AGC circuit is disabled during write
mode operations.
Appendix A
Once the sector presently passing beneath the heads
matches the addressed sector, the sector compare flip-flop
on microprocessor PCA-A2 will be clocked. When clocked
during a read mode operation, the sector compare flip-flop
will be clocked set and the sector compare signal will
become active (SC
=
1) to enable the read/write system for
a data transfer. Sector compare will remain active until
the end of the addressed sector is forced (count 817) or the
READ command is dropped.
With the disc drive selected (SEL
=
1) and the read system
enabled (URG
=
1), the zero crossing detector and line
driver are both enabled. The zero crossing detector will
produce a pulse for positive- or negative-going zero cross-
ings. These pulses are transferred via bidirectional data
lines to the data separator in the controller. (See para-
graph A-17.)
A-54. WRITE MODE OPERATION. Data is
written by passing a current through the read/write
winding in the selected head. This generates a flux field
across the gap. The flux field magnetizes the iron oxide
particles bound to the surface of the disc. The writing
process orients the poles of each magnetized particle to
permanently store the direction of the flux field as the
oxide passes beneath the head. The direction of the flux
field is a function of the write current polarity. Data is
written by reversing the write current through the head
windings. This change in write current polarity switches
the direction of the flux field across the gap. Erasing old
data is accomplished by writing over any data which may
have been previously written on the disc.
As in a read operation, the sector compare flip-flop must
be clocked set and the sector compare signal must be
active (SC
=
1) to enable the read/write system for a data
transfer. Sector compare will remain active until the end
of the addressed sector is forced (count 816) or the WRITE
command is dropped.
With the disc drive selected (SEL
=
1) and the write
system enabled (UWG
=
1), the line receiver on drive
control PCA-A4 is enabled to accept data from the control-
ler via the bidirectional data lines. Data formatting is
performed by circuits in the controller. (See paragraph
A-16.) The data pulses produced by the line receiver toggle
the write toggle logic to supply two complimentary write
data signals (WDA and WDB) once the write mode of
operation has been enabled. The write mode is enabled
when the disc drive is selected (SEL = 1), the write system
is enabled (UWG
=
1), no write faults exist (WFLT
=
0),
and the read only mode is disabled (R02
=
0).
The read only mode inhibits a write operation and thus
prevents data from being written onto any data surface of
the disc pack. The read only mode is selected when the
READ ONLY switch is set to READ ONLY. The READ
ONLY lamp will light and the read only status bit will
become active (status bit 7
=
1) to signify that the read
only mode has been selected.
A-25