HP 7925D Service Manual page 207

Appendix A
When the write signal is active (WRITE
=
1) and the URG
and ACRY signals are both inactive (URG and ACRY
=
0)
which signifies that the read mode is disabled and the
heads are settled over a legal cylinder, the WEN signal
will become active (WEN
= 1)
to enable the write mode.
Once enabled, the the read/write mode FET switches will
disconnect the head select diodes from the. preamplifier
stage. In addition, it will enable the switchable write cur-
rent source to produce write current to the head windings.
The amount of write current produced is controlled by the
programmable write current sink.
The three most significant bits of the cylinder address are
coupled from servo PCA-A3 to the input of the program-
mable write current sink on RlW preamplifier PCA-A6.
This information is used to modify the write current via
the programmable write current sink. Seven write current
zones ensure proper saturation for best head resolution.
Write current is reduced by 3.50 milliamperes for each 128
cylinder increment from cylinder zero. Maximum write
current is available at the outer cylinders and it is pro-
gressively reduced as the heads are moved toward the
inner cylinders. This will optimize the write current for
the changing relative velocity between the heads and
media as cylinder radius decreases. Table A-4 lists the
reduction in write current as a function of the cylinder
address.
Table A-4. Write Current Reduction vs.
Cylinder Address
REDUCTION IN
CYLINDER DWA DWB DWe WRITE CURRENT
(rnA peak)
0 - 127
a a a
a
128 - 255
a a
1
3.50
256 - 383
a
1
a
7.0
384- 511
a
1
1 10.5
512 - 639
1
a a
14.0
640- 767 1
a
1 17.5
768- 822
1 1
a
21.0
The programmable write current sink draws current from
the selected head through the write current switches.
Each write current switch is in series with one of the head
windings. The complementary write data lines (WDA and
WDB) alternately control these write current switches.
This selects the head winding through which the write
current will pass. Changing the write current from one
winding to the other reverses the flux field at the gap in
the ferrite core. This changes the direction of the magne-
tization of the oxide particles bound to the surface of the
disc, thereby writing a data bit.
A-55. READ/WRITE FAULT DETECTION. As
previously mentioned, the multiple heads selected detec-
tor continuously monitors the center taps of each head
winding, and if more than one head is selected, a destruc-
tive MH fault is declared. In addition, the ac write current
A·26
7925
detector continuously monitors the write current paths,
and if the absence of alternating write current is sensed, a
destructive W. AC fault is declared. The dc write current
detector continuously monitors the output of the switch-
able write current source, and if dc write current is being
applied to the head windings and the disc drive is not in
the write mode, a destructive DC. W fault is declared.
The state of the ACRY signal is continuously monitored,
and ifhead movement is detected during the write mode, a
non-destructive W. AR fault is declared. The state of the
URG signal is continuously monitored, and if the read and
write modes are simultaneously enabled, a non-
destructive R. W fault is declared. Whenever one of these
read/write fault conditions is detected, a latch on' drive
control PCA-A4 will be set, an LED will light, subsequent
read/write faults will be inhibited, the write mode will be
terminated, and all heads will be disabled.
A-56. FAULT DETECTION SYSTEM
The fault detection system (see figure A-21) consists of
circuits on data PCA-Al, microprocessor PCA-A2, servo
PCA-A3, drive control PCA-A4, spindle logic PCA-A8,
power and motor regulator (PMR) PCA-A9, and fault indi-
cator PCA-AI2. All communication between card cage
PCA's occurs via motherboard PCA-A 7 and interconnect-
ing cables. Spindle logic PCA-A8 and PMR PCA-A9 com-
municate with the other PCA's through the main harness.
Fault indicator PCA-AI2 communicates with drive con-
trol PCA-A4 through a separate interconnecting cable.
The purpose of the fault detection system is to continually
monitor various conditions within the disc drive, and light
fault indicators, retract the heads, and brake spindle rota-
tion when a fault is detected. Included in the following are
discussions relative to illegal address, timeout, AGC, car-
riage back, interlock, and read/write fault detection.
A-57. ILLEGAL ADDRESS DETECTION. A circuit
servo PCA-A3 continually monitors the internal control
bus in the disc drive for illegal cylinder addresses.
Whenever this condition exists, the disc drive will make
seek check (status bit 3
=
1) available in its status word
and it will not clock the illegal address into the appro-
priate register.
The internal control bus bits DO through D9 are continu-
ally monitored by the illegal cylinder address detector on
servo PCA-A3. If a cylinder address greater than 822 is
detected, the ICA signal will become active (ICA
=
1).
This will inhibit the illegal cylinder address from being
clocked into the new cylinder address register (see
figure A-21). The seek check flip-flop will be clocked set on
the leading edge of the decoded SEEK command. The seek
check flip-flop is reset by NDPS whenever the power-on
sequence is initiated (lLF
=
1), the RUN/STOP switch is
set to RUN (RUN
=
1), or a CPS command is decoded
(CPS
=
1). In addition, the seek check flip-flop is reset by
CYL whenever the seek home command is active
(SKH = 0) or a seek to a legal cylinder address command
is decoded.