HP 7925D Service Manual page 257

Appendix A
7925
A-96. IDLE STATES
A-97. CONTROLLER SECONDARIES
The
controll~r
can interpret the thirteen secondaries
listed in table A-15. (For a detailed description of these
secondaries, refer to the HP 13365 Integrated Disc Con-
troller Programming Guide, part no. 13365-90901.) The
two CRC secondaries listed in table A-15 are not im-
plemented in current versions of the controller and are
included for reference only.
The controller has three idle states, where it is waiting to
perform an operation (command or secondary). Idle State 1
(analogous to the Command Wait Loop in the HP 13037
Disc Controller) is entered at the normal or error comple-
tion of all secondaries except the END command and the
RETURN DSJ BYTE secondary. In Idle State 1, the con-
troller will respond to any parallel poll conducted on the
HP-IB but will not report the disc drive being unloaded
nor allow self-test to be invoked via the self-test START
switch located at the rear of the disc drive. These
condi~
tions arc reversed in Idle State 2 (analogous to the HP
13037 Disc Controller Poll Loop). That is, the controller
will not respond to a parallel poll except when a disc drive
is unloaded, but it will respond to the self-test START
switch. Idle State 3, entered after a self test or SEC-
ONDARY (HARD) CLEAR is performed, is similar to Idle
State 2 except that the controller also generates a parallel
poll response (PPR). Since a self test is automatically
performed at power-on or whenever the disc drive is
loaded, Idle State 3 will be entered at these times also.
8 7 6 5 4 3 2 1
~9xxxxl
The controller expects the last data byte sent to it during
any listen sequence to be tagged with the EOI bit. When
the controller is addressed to talk, any data byte tagged
with EOI usually indicates an error condition in the con-
troller. The only exceptions are the READ LOOPBACK
RECORD secondary and the CRC secondary.
Any secondary other than those described will generate an
I/O program error status and set the device-specified jump
(DSJ) byte to 1 (error). I/O program error status and DSJ
byte
=
1 also result if any byte tagged with ATN is re-
ceived with incorrect (even) parity and the parity freeze
option of the PHI is not enabled.
ity bit in bit 8 of all controller-in-charge primaries and
secondaries. The PHI chip mayor may not freeze the
bus when parity is not odd. This is a programmable
feature set by bit 1 in the data byte of a System 300
CLEAR command. DIC is used to distinguish between
"data-type" and "control-type" secondaries (D/C
=
all), and XXXX is a modifier field which defines the
particular operation to be performed. Note in table
A-15 that the same secondary can be used to perform
different operations, depending on whether the asso-
ciated primary is an address to talk or an address to
listen.
The PHI chip, when processing a secondary, changes the 1
sent in bit 6 to a listen/talk = 0/1, depending on the sense
of the associated primary. Thus, the controller can deter-
mine the proper interpretation of the secondary.
CRC. A dummy cyclic redundancy check which is
contained in the controller vocabulary to provide up-
ward compatibility with future versions of the PHI
chip capable of checking for errors in the data.
•
The general form of the secondary as transmitted over
the HP-IB, is as shown in fjgure A-27. P is an odd par-
7300-113
Figure A-27. General Form of Secondary
A-84