HP 7925D Service Manual page 190

Appendix A 7925
Table A-I. Controller Mnemonics (Continued)
MNEMONIC
SIGNAL
IL Interlock
INPHI Input from PHI chip
INTCW Internal Control Word
ISTSW Initiate Self-Test Switch
LED 0-3
Light Self-Test LED
LSB Least Significant Byte
MSB Most Significant Bit
NDAC Data Accepted (ground true)
NRFD Ready for Data (ground true)
NTORE Not Output Register Empty
OE Output Enable
OFIFO Output to FIFO
OPHI Output to PHI
OVRFLO Overflow
OVRUN Overrun
PHEAD Physical Head
PHICW PHI Control Word
PON Power on Preset
PSECT Physical Sector
RAR 0-11 ROM Address Register
RC Read Clock
RCP Read Clock Pulses
RD Read Data
REN Remote Enable
RES Reset
ROM 0-23 ROM Output Memory
ROR 0-23 ROM Output Register
A-8
FUNCTION
Completes interlock path on motherboard PCA-A7.
Enables transfer of data from PHI to ALU.
Enables loading of Internal Control Word output register.
This register sets up data path operations.
Flag from self-test panel to microprocessor which starts self-
test sequence.
Four lines from Self-Test output register to self-test panel.
Flag indicating that least significant bit of ALU output byte
is a one.
Flag indicating that most significant bit of ALU output byte
is a one.
Bidirectional HP-IB control line.
Bidirectional HP-IB control line.
Flag indicating presence of data in FIFO.
Enables transfer of data from ALU to bidirectional buffer
over output data bus.
Enables data transfer from ALU to FIFO via bidirectional
buffer.
Enables data transfer from ALU to PHI chip via bidirectional
buffer.
Flag indicating an overflow in ALU during an arithmetic
operation.
Flag indicating either FIFO going empty during a write oper-
ation or FI FO overflowing during a read operation. (Indi-
cates failure of HP-IB or CPU to keep up.)
Enables head register to pass current head address to ALU
via input data bus.
Enables data to pass from ALU to PHI Control Word register,
setting up parameters for transfer to or from PHI chip.
Connects to disc drive NDPS line and resets microcode.
Enables number of sector currently under heads to be trans-
mitted from Physical Sector register to ALU.
Twelve-bit address of next microcode word.
A 7.5-MHz read clock generated by separator circuitry during
a read or verify operation.
Special read clock for word counter. Not enabled during for-
matter/separator loopback self test when write clock only is
" used.
Serial data from separator during read or verify operations.
A bidirectional HP-IB control line.
Signal generated from PON to clear various registers in
microprocessor.
Output of currently addressed microcode memory location.
Latched microcode word representing current microprocessor
instruction.