HP 7925D Service Manual page 38

7925
In the first condition, the state of the AeRY signal is
continually monitored. If the heads are not settled over
the specified cylinder (ACRY
=
1) during the write mode
(WRITE
=
1) and no other write faults exist (WFLT
=
1),
a W
0
AR fault is declared. When a W
0
AR fault is
detected, the following events will occur:
-
- -
oW. AR fault flip-flop is set (W
0
AR
0
WFLT
=
1).
o WRFL signal becomes active (WRFL
=
0).
- - - -
o W
0
AR fault LED lights (WRFL
=
0).
o NDWF signal becomes active (NDWF
=
0).
o WFLT signal becomes active (WFLT
=
0).
o Subsequent read/write faults are inhibited
(WFLT
=
0).
o DRIVE FAULT lamp lights (FLTL
=
0).
o Drive fault status bit becomes active (status bit 4
=
1).
The W
0
AR fault flip-flop is reset by NDPS whenever the
power-on sequence is initiated (ILF
=
1), the RUN/STOP
switch is set to RUN (RUN
=
1), or a CPS command is
decoded (CPS
=
1).
In the second condition, the state of the URG signal is
continually monitored. If the URG signal becomes active
(URG
=
1) during the write mode (WRITE
=
1) and no
other write faults exist (WFLT
=
1), a R • W fault is
declared. When a RoW fault is detected, the following
events will occur:
oRo W fault flip-flop is set (R
0
W
0
WFLT
=
1).
o RWFL signal becomes active (RWFL
=
0).
o R o W fault LED lights (RWFL
=
0).
o NDWF signal becomes active (NDWF
=
0).
o WFLT signal becomes active (WFLT
=
0).
o Subsequent read/write faults are inhibited
(WFLT
=
0).
• DRIVE FAULT lamp lights (FLTL
=
0).
• Drive fault status bit becomes active (status bit 4
=
1).
The R • W fault flip-flop is reset by NDPS whenever the
power-on sequence is initiated (lLF
=
1), the RUN/STOP
switch is set to RUN (RUN
=
1), or a CPS command is
decoded (CPS
=
1).
1-60. Destructive Write Faults. The three fault
conditions classified as destructive are:
Theory of Operation
• A write gate without any alternating write current
(W. AC).
o More than one head selected (MH).
o DC write current without a write gate (DC. W).
In the first condition, the state of the ACW signal is
continually monitored. If the ACW signal remains inac-
tive (ACW
=
0) during the write mode (WRITE
=
1) and
no write faults exist (WFLT
=
1), a W • AC fault is de-
clared. When a W
0
AC fault is detected, the following
events will occur:
o W
0
AC fault flip-flop is set (W • AC • WFLT
=
1).
o WAFL signal becomes active (WAFL
=
0).
o W
0
AC fault LED lights (WAFL
=
0).
o DWF signal becomes active (DWF
=
0).
o WFLT signal becomes active (WFLT
=
0).
o Subsequent read/write faults are inhibited
(WFLT
=
0).
o Heads are unloaded. Refer to table 1-6, steps 1 through
8, for the specific events.
The W
0
AC fault flip-flop is reset by DPS whenever the
power-on sequence is initiated (lLF
=
1) or the RUN/
STOP is set to RUN (RUN
=
1).
In the second condition, the state of the MHS signal is
continually monitored. If the MHS signal becomes active
(MHS
=
0) and no other write faults exist (WFLT
=
1), a
MH fault is declared. When a MH fault is detected, the
following events will occur:
• MH fault flip-flop is set (MHS • WFLT
=
1).
• MHFL signal becomes active (MHFL
=
0).
o MH fault LED lights (MHFL
=
0).
o DWF signal becomes active (DWF
=
0).
• WFLT signal becomes active (WFLT
=
0).
• Subsequent read/write faults are inhibited
(WFLT
=
0).
• Heads are unloaded. Refer to table 1-6, steps 1 through
8, for the specific events.
The MH fault flip-flop is reset by DPS whenever the
power-on sequence is initiated (ILF
=
1) or the RUN/
STOP switch is set to RUN (RUN
=
1).
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