Interlocks - Omron SYSMAC CVM1 Series Operation Manual

Branching Instruction Lines

4-5-2 Interlocks

0000
00
0000
01
0000
02
82
The problem of storing execution conditions at branching points can also be
handled by using the INTERLOCK (IL(002)) and INTERLOCK CLEAR
(ILC(003)) instructions to eliminate the branching point completely while allow-
ing a specific execution condition to control a group of instructions. The INTER-
LOCK and INTERLOCK CLEAR instructions are always used together.
When an INTERLOCK instruction is placed before a section of a ladder pro-
gram, the execution condition for the INTERLOCK instruction will control the
execution of all instruction up to the next INTERLOCK CLEAR instruction. If the
execution condition for the INTERLOCK instruction is OFF, all right-hand
instructions through the next INTERLOCK CLEAR instruction will be executed
with OFF execution conditions to reset the entire section of the ladder diagram.
The effect that this has on particular instructions is described in 5-8 INTERLOCK
and INTERLOCK CLEAR - IL(002) and ILC(003).
Diagram B can also be corrected with an interlock. Here, the conditions leading
up to the branching point are placed on an instruction line for the INTERLOCK
instruction, all of lines leading from the branching point are written as separate
instruction lines, and another instruction line is added for the INTERLOCK
CLEAR instruction. No conditions are allowed on the instruction line for INTER-
LOCK CLEAR. INTERLOCK and INTERLOCK CLEAR does not use operands.
If CIO 000000 is ON in the revised version of diagram B, above, the status of
CIO 000001 and that of CIO 000002 would determine the execution conditions
for instructions 1 and 2, respectively. Because CIO 000000 is ON, this would
produce the same results as ANDing the status of each of these bits. If
CIO 000000 is OFF, the INTERLOCK instruction would produce an OFF execu-
tion condition for instructions 1 and 2 and then execution would continue with the
instruction line following the INTERLOCK CLEAR instruction.
(002)
Address
IL
00000
00001
Instruction 1
00002
00003
Instruction 2
00004
00005
(003)
ILC
00006
Section 4-5
Instruction Operands
LD 000000
IL(002) ---
LD 000001
Instruction 1
LD 000002
Instruction 2
ILC(003) ---