Item
Address hold time
Address setup time
System cycle time 1
System cycle time 2
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse Read
time
Write
Enable LOW pulse Read
time
Write
Item
Address hold time
Address setup time
System cycle time 1
System cycle time 2
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse Read
time
Write
Enable LOW pulse Read
time
Write
*1 The input signal rise time and fall time (
t
extremely fast, (
r
*2 All timing is specified using 20% and 80% of V
t
t
and
*3
EWLW
EWLR
Rev.2.1
Signal
Symbol
t
A0
t
t
A0
t
t
D0 to D7
t
t
t
t
E
t
t
E
t
Signal
Symbol
t
A0
t
t
A0
t
t
D0 to D7
t
t
t
t
E
t
t
E
t
t
) ≤ (
t
t
t
+
–
f
CYCH (L) 6
EWLW
are specified as the overlap between CS1 being LOW (CS2 = HIGH) and E.
Table 30
(V
DD
Condition
AH6
AW6
CYCH6
CYCL6
DS6
DH6
C
= 100 pF
ACC6
L
OH6
EWHR
EWHW
EWLR
EWLW
Table 31
(V
DD
Condition
AH6
AW6
CYCH6
CYCL6
DS6
DH6
C
= 100 pF
ACC6
L
OH6
EWHR
EWHW
EWLR
EWLW
t
,
) is specified at 15 ns or less. When the system cycle time is
r
f
) ≤ (
t
t
t
–
) for (
+
EWHW
r
f
as the reference.
DD
EPSON
S1D10605 Series
= 2.4 V to 3.0 V, Ta = –40 to +85°C )
Rating
Min.
Max.
0
—
0
—
450
—
450
—
60
—
20
—
—
230
10
150
180
—
90
—
90
—
90
—
= 1.8 V to 2.4 V, Ta = –40 to +85°C )
Rating
Min.
Max.
0
—
0
—
600
—
600
—
80
—
30
—
—
280
10
200
240
—
120
—
120
—
120
—
t
t
t
–
–
CYCH (L) 6
EWLR
EWHR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
) are specified.
63