Epson S1D10605 Series Manual page 63

Item
Address hold time
Address setup time
System cycle time 1
System cycle time 2
Control LOW pulse width (Write)
Control LOW pulse width (Read)
Control HIGH pulse width (Write)
Control HIGH pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
Item
Address hold time
Address setup time
System cycle time 1
System cycle time 2
Control LOW pulse width (Write)
Control LOW pulse width (Read)
Control HIGH pulse width (Write)
Control HIGH pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
*1 The input signal rise time and fall time (
t
extremely fast, (
r
*2 All timing is specified using 20% and 80% of V
t t
and
*3
CCLW CCLR
being at the LOW level.
Rev.2.1
Signal
A0
A0
WR
RD
WR
RD
D0 to D7
Signal
A0
A0
WR
RD
WR
RD
D0 to D7
t
) ≤ (
t t t
+ –
f CYCL (H) 8 CCLW
are specified as the overlap between CS1 being LOW (CS2 = HIGH) and WR and RD
Table 27
(V
DD
Symbol Condition
t
AH8
t
AW8
t
CYCL8
t
CYCH8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
C = 100 pF
ACC8 L
t
OH8
Table 28
(V
DD
Symbol Condition
t
AH8
t
AW8
t
CYCL8
t
CYCH8
t
CCLW
t
CCLR
t
CCHW
t
CCHR
t
DS8
t
DH8
t
C = 100 pF
ACC8 L
t
OH8
t
, ) is specified at 15 ns or less. When the system cycle time is
r f
) ≤ (
t t t
– ) for ( +
CCHW r f
as the reference.
DD
EPSON
S1D10605 Series
= 2.4 V to 3.0 V, Ta = –40 to +85°C )
Rating
Min. Max.
0 —
0 —
450 —
450 —
90 —
180 —
90 —
90 —
60 —
20 —
— 230
10 150
= 1.8 V to 2.4 V, Ta = –40 to +85°C )
Rating
Min. Max.
0 —
0 —
600 —
600 —
120 —
240 —
120 —
120 —
80 —
30 —
— 280
10 200
t t t
– –
CYCL (H) 8 CCLR CCHR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
) are specified.
61