Epson S1D10605 Series Manual page 20

S1D10605 Series
Display Data RAM
Display Data RAM
The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page × 8 bit +1) × 132 bit structure.
It is possible to access the desired bit by specifying the page address and the column address.
Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display
common direction, there are few constraints at the time of display data transfer when multiple S1D10605 series chips
are used, thus and display structures can be created easily and with a high degree of freedom.
Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which
is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM
is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as
flickering).
The Page Address Circuit
As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The
page address must be specified again when changing pages to perform access.
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display
data D0 is used.
The Column Addresses
As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The
specified column address is incremented (+1) with each display data read/write command. This allows the MPU display
data to be accessed continuously.
Moreover, the incrementation of column addresses stops with 83H. Because the column address is independent of the
page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify
both the page address and the column address.
Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to
reverse the relationship between the display data RAM column address and the segment output. Because of this, the
constraints on the IC layout when the LCD module is assembled can be minimized.
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents
of the display data RAM are displayed. Using the display start line address set command, what is normally the top line
of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63
output for S1D10605 Series, COM47 output for S1D10606 Series, COM31 output for the S1D10607, COM53 output
for the S1D10608 and COM51 output for the S1D10609 Series when the common output mode is reversed. The display
area is a 65 line area for the S1D10605 Series, a 49 line area for the S1D10606, a 33 line area for the S1D10607, a 55
line area for the S1D10608 and a 53 line area for the S1D10609 from the display start line address.
If the line addresses are changed
swapping, etc. can be performed.
18
D0 0 1 1 1 0
D1 1 0 0 0 0
D2 0 0 0 0 0
D3 0 1 1 1 0
D4 1 0 0 0 0
—
Display data RAM
SEG
SEG0
Output
ADC "0" 0 (H) →
(D0) "1" 83 (H) ← Column Address ← 0 (H)
dynamically using the display start line address set command, screen scrolling, page
COM0
COM1
COM2
COM3
COM4
—
Liquid crystal display
Figure 3
Table 4
SEG 131
Column Address → 83 (H)
EPSON
Rev.2.1