Epson S1D10605 Series Manual page 23

When multiple S1D10605 Series chips are used, the slave chips must be supplied the display timing signals (FR, CL,
DOF) from the master chip[s].
Table 5 shows the status of the FR, CL, and DOF signals.
Master (M/S = HIGH) The internal oscillator circuit is enabled (CLS = HIGH) Output Output
Slave (M/S = LOW) Set the CLS pin to the same level as with the master. Input
The Common Output Status Select Circuit
In the S1D10605 Series chips, the COM output scan direction can be selected by the common output status select
command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be
minimized.
Status
S1D10605
*****
COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51
Normal
Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0
The Liquid Crystal Driver Circuits
These are a 197-channel (S1D10605 Series), a 181-channel (S1D10606 Series) multiplexers 165-channel (S1D10607
Series), a 187-channel (S1D10608 Series). and a 185-channel (S1D10609 Series) that generate four voltage levels for
driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the
liquid crystal drive voltage output.
Figure 6 shows examples of the SEG and COM output wave form.
Rev.2.1
Operating Mode
The internal oscillator circuit is disabled (CLS = LOW) Output Input
S1D10606
*****
Table 5
Table 6
COM Scan Direction
S1D10607 S1D10608
*****
EPSON
S1D10605 Series
FR CL DOF
Output
Output
Input Input
Input Input Input
S1D10609
***** *****
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