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S1D10605 Series
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver
circuit from the display data RAM.
Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control
only the data within the latch, they do not change the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = HIGH
and CLS = HIGH.
When CLS = LOW the oscillation stops, and the display clock is input through the CL terminal.
Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the display data latch
circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the
display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits
is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data
RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering)
on the display.
Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current
signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as
is shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive wave form (S1D10605
64
65 1
CL
FR
COM0
COM1
RAM
DATA
SEGn
20
2
3
4
5
6
*****
60 61 62 63 64 65 1
Figure 5
EPSON
)
2
3
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6
V
V
V
V
V
V
V
V
V
V
V
V
Rev.2.1
DD
1
4
5
DD
1
4
5
DD
2
3
5
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