Epson S1D13506 LCD Controller Manuals

Manuals and User Guides for Epson S1D13506 LCD Controller. We have 1 Epson S1D13506 LCD Controller manual available for free PDF download: Technical Manual

Epson S1D13506 Technical Manual (712 pages)

Color LCD/CRT/TV Controller

Brand: Epson | Category: Controller | Size: 6.51 MB

Table of Contents

9
- Millenia Tower Singapore
  3
- Riesstrasse
  3
- Issue Date: 02/03/26 Page
  11
List of Tables

15
Table of Contents

237
- 3 Memory Models
  
  250
- 4 Look-Up Table (LUT)
  
  253
  - Registers
    253
  - Look-Up Table Organization
    254
    
    Color Modes
    255
    
    Gray Shade Modes
    258
- 5 Virtual Displays
  
  260
  - Virtual Display
    260
    
    Registers
    261
    
    Examples
    262
  - Panning and Scrolling
    264
    
    Registers
    265
    
    Examples
    267
- 6 Power Save Mode
  
  269
  - Overview
    269
  - Registers
    269
    
    Enabling Power Save Mode
    269
    
    Power Save Status Bits
    270
    
    DRAM Refresh Selection
    271
- 7 LCD Power Sequencing
  
  272
  - Automatic Sequencing
    272
  - Manual Sequencing
    272
    
    Disabling the LCD Panel
    273
    
    Enabling the LCD Panel
    273
    
    Registers
    273
- 8 Hardware Cursor/Ink Layer
  
  274
  - Introduction
    274
  - Registers
    275
  - Initialization
    281
    
    Memory Considerations
    281
    
    Examples
    282
  - Writing Cursor/Ink Layer Images
    284
    
    Hardware Cursor/Ink Layer Data Format
    284
    
    Cursor Image
    285
    
    Ink Layer Image
    286
  - Cursor Movement
    287
    
    Move Cursor in Landscape Mode (no Rotation)
    287
    
    Move Cursor in Swivelview 180° Rotation
    288
    
    Move Cursor in Swivelview 90° Rotation
    288
    
    Move Cursor in Swivelview 270° Rotation
    289
- 9 Swivelview
  
  290
  - S1D13506 Swivelview
    290
  - Registers
    290
  - Limitations
    292
  - Examples
    293
  - Simultaneous Display Considerations
    294
  - Registers
    295
  - Bitblt Descriptions
    302
    
    Write Blit with ROP
    303
    
    Color Expand Bitblt
    305
    
    Color Expand Bitblt with Transparency
    310
    
    Solid Fill Bitblt
    310
    
    Move Bitblt in a Positive Direction with ROP
    311
    
    Move Bitblt in Negative Direction with ROP
    313
    
    Transparent Write Blit
    315
    
    Transparent Move Bitblt in Positive Direction
    317
    
    Pattern Fill Bitblt with ROP
    319
    
    Pattern Fill Bitblt with Transparency
    321
    
    Move Bitblt with Color Expansion
    322
    
    Read Blit
    324
    
    Transparent Move Blit with Color Expansion
    324
  - S1D13506 Bitblt Synchronization
    326
  - S1D13506 Bitblt Known Limitations
    328
  - Sample Code
    328
- 11 CRT/TV Considerations
  
  329
  - CRT Considerations
    329
    
    DAC Output Level Selection
    329
    
    Generating CRT Timings with 13506CFG
    329
    
    Examples
    330
    
    NTSC Timings
    330
    
    PAL Timings
    330
    
    TV Considerations
    330
    
    Examples
    331
    
    TV Filters
    331
    
    Simultaneous Display
    332
- 12 Mediaplug
  
  333
  - Programming
    333
  - Considerations
    333
- 13 Identifying the S1D13506
  
  335
- 14 Hardware Abstraction Layer (HAL)
  
  336
  - API for 13506HAL
    336
  - Initialization
    341
    
    General HAL Support
    344
    
    Advance HAL Functions
    349
    
    Surface Support
    351
    
    Register Access
    354
    
    Memory Access
    356
    
    Color Manipulation
    358
    
    Virtual Display
    362
    
    Drawing
    364
    
    Hardware Cursor
    370
    
    Ink Layer
    377
    
    PCI Support
    383
  - Porting LIBSE to a New Target Platform
    384
    
    Building a Complete Application for the Target Example
    385
    
    Building the LIBSE Library for SH3 Target Example
    385
- 15 Sample Code
  
  386
Table of Contents

393
- 13506Cfg
  395
- S1D13506 Supported Evaluation Platforms
  395
- Installation
  396
- Usage
  396
- 13506CFG Configuration Tabs
  397
  - General Tab
    397
  - Preferences Tab
    399
  - Memory Tab
    400
  - Clocks Tab
    402
  - Panel Tab
    406
  - CRT/TV Tab
    410
  - Registers Tab
    412
- 13506CFG Menus
  413
  - Open
    413
  - Save
    414
  - Save as
    414
  - Configure Multiple
    415
  - Export
    416
  - Enable Tooltips
    417
  - ERD on the Web
    417
  - About 13506CFG
    417
- Comments
  417
  - Installation Guide
    513
  - User Manual
    521
Table of Contents

523
- List of Figures
  525
- List of Tables
  525
- 1 Introduction
  
  527
- 2 Features
  
  528
- 3 Installation and Configuration
  
  529
  - Configuration DIP Switches
    529
  - Configuration Jumpers
    530
- 4 Technical Description
  
  531
  - PCI Bus Support
    531
    
    On-Board PCI Configuration Registers
    532
    
    Utility Software
    532
  - Non-PCI Host Interface Support
    533
    
    CPU Interface Pin Mapping
    533
    
    CPU Bus Connector Pin Mapping
    534
  - LCD Support
    536
    
    LCD Interface Pin Mapping
    537
    
    16-Bit Passive Color Panel Support with Mediaplug Enabled
    538
    
    Buffered LCD Connector
    538
    
    Adjustable LCD Panel Negative Power Supply
    539
    
    Adjustable LCD Panel Positive Power Supply
    539
  - CRT/TV Support
    540
    
    CRT Support
    540
    
    CRT/TV Interface Pin Mapping
    540
    
    TV Support
    540
  - Mediaplug Interface
    541
  - Clock Synthesizer and Clock Options
    542
    
    Clock Programming
    542
- 5 References
  
  543
  - Documents
    543
  - Document Sources
    543
- 6 Parts List
  
  544
- 7 Schematic Diagrams
  
  546
- 8 Technical Support
  
  553
  - EPSON Lcd/Crtcontrollers (S1D13506)
    553
Table of Contents

557
- 1 Introduction
  
  561
- 2 Interfacing to the PC Card Bus
  
  562
  - The PC Card System Bus
    562
    
    Memory Access Cycles
    562
    
    PC Card Overview
    562
- 3 S1D13506 Host Bus Interface
  
  565
  - PC Card Host Bus Interface Pin Mapping
    565
  - PC Card Host Bus Interface Signals
    566
- 4 PC Card to S1D13506 Interface
  
  567
  - Hardware Description
    567
  - S1D13506 Hardware Configuration
    569
  - Performance
    569
  - Register/Memory Mapping
    570
- 5 Software
  
  571
- 6 References
  
  572
  - Documents
    572
  - Document Sources
    572
- 7 Technical Support
  
  573
  - Epson LCD/CRT Controllers (S1D13506)
    573
  - PC Card Standard
    573
  - Power Consumption
    575
Host Bus Interface Signal Descriptions

583
- 1 Introduction
  
  587
- 2 Interfacing to the VR4102/VR4111
  
  588
  - The NEC VR4102/VR4111 System Bus
    588
    
    Overview
    588
    
    LCD Memory Access Cycles
    589
- 3 S1D13506 Host Bus Interface
  
  590
  - Host Bus Interface Pin Mapping
    590
  - Host Bus Interface Signal Descriptions
    591
- 4 VR4102/VR4111 to S1D13506 Interface
  
  592
  - Hardware Description
    592
  - S1D13506 Hardware Configuration
    593
- 5 Software
  
  594
- 6 References
  
  595
  - Documents
    595
  - Document Sources
    595
- 7 Technical Support
  
  596
  - EPSON LCD/CRT Controllers (S1D13506)
    596
  - NEC Electronics Inc. (VR4102/VR4111)
    596
Table of Contents

599
- 1 Introduction
  
  603
- 2 Interfacing to the MPC821
  
  604
  - The Mpc8Xx System Bus
    604
  - MPC821 Bus Overview
    604
    
    Normal (Non-Burst) Bus Transactions
    605
    
    Burst Cycles
    606
  - Memory Controller Module
    607
    
    General-Purpose Chip Select Module (GPCM)
    607
    
    User-Programmable Machine (UPM)
    608
- 3 S1D13506 Host Bus Interface
  
  609
  - Powerpc Host Bus Interface Pin Mapping
    609
  - Powerpc Host Bus Interface Signals
    610
- 4 MPC821 to S1D13506 Interface
  
  611
  - Hardware Description
    611
  - Hardware Connections
    612
  - S1D13506 Hardware Configuration
    614
  - Register/Memory Mapping
    614
  - MPC821 Chip Select Configuration
    615
  - Test Software
    616
- 5 Software
  
  617
- 6 References
  
  618
  - Documents
    618
  - Document Sources
    618
- 7 Technical Support
  
  619
  - EPSON LCD/CRT Controllers (S1D13506)
    619
  - Motorola MPC821 Processor
    619
Table of Contents

623
- 1 Introduction
  
  627
- 2 Interfacing to the PR31500/PR31700
  
  628
- 3 S1D13506 Host Bus Interface
  
  629
  - PR31500/PR31700 Host Bus Interface Pin Mapping
    629
  - PR31500/PR31700 Host Bus Interface Signals
    630
- 4 Direct Connection to the Philips PR31500/PR31700
  
  631
  - Hardware Description
    631
  - S1D13506 Configuration
    632
  - Memory Mapping and Aliasing
    633
- 5 System Design Using the IT8368E PC Card Buffer
  
  634
  - Hardware Description
    634
  - IT8368E Configuration
    635
  - S1D13506 Configuration
    635
- 6 Software
  
  636
- 7 References
  
  637
  - Documents
    637
  - Document Sources
    637
- 8 Technical Support
  
  638
  - EPSON LCD/CRT Controllers (S1D13506)
    638
  - Philips MIPS PR31500/PR31700 Processor
    638
  - Ite It8368E
    638
Table of Contents

641
- 1 Introduction
  
  645
- 2 Interfacing to the TX3912
  
  646
- 3 S1D13506 Host Bus Interface
  
  647
  - TX3912 Host Bus Interface Pin Mapping
    647
  - TX3912 Host Bus Interface Signals
    648
- 4 Direct Connection to the Toshiba TX3912
  
  649
  - Hardware Description
    649
  - S1D13506 Configuration
    650
  - Memory Mapping and Aliasing
    651
- 5 System Design Using the IT8368E PC Card Buffer
  
  652
  - Hardware Description
    652
  - IT8368E Configuration
    653
  - S1D13506 Configuration
    653
- 6 Software
  
  654
- 7 References
  
  655
  - Documents
    655
  - Document Sources
    655
- 8 Technical Support
  
  656
  - EPSON LCD/CRT Controllers (S1D13506)
    656
  - Toshiba MIPS TX3912 Processor
    656
  - Ite It8368E
    656
Table of Contents

659
- 1 Introduction
  
  663
  - The NEC VR4121 System Bus
    664
    
    Overview
    664
    
    LCD Memory Access Cycles
    665
- 3 S1D13506 Host Bus Interface
  
  666
  - Host Bus Interface Pin Mapping
    666
  - Host Bus Interface Signal Descriptions
    667
- 4 VR4121 to S1D13506 Interface
  
  668
  - Hardware Description
    668
  - S1D13506 Configuration
    669
  - Memory Mapping and Aliasing
    670
- 5 Software
  
  671
- 6 References
  
  672
  - Documents
    672
  - Document Sources
    672
- 7 Technical Support
  
  673
  - Epson LCD/CRT Controllers (S1D13506)
    673
  - NEC Electronics Inc. (VR4121)
    673
Table of Contents

677
- 1 Introduction
  
  681
- 2 Interfacing to the NEC V832
  
  682
  - The NEC V832 System Bus
    682
    
    Overview
    682
    
    Access Cycles
    683
- 3 S1D13506 Host Bus Interface
  
  684
  - Host Bus Interface Pin Mapping
    684
  - Host Bus Interface Signal Descriptions
    685
- 4 V832 to S1D13506 Interface
  
  686
  - Hardware Description
    686
  - S1D13506 Hardware Configuration
    687
  - NEC V832 Configuration
    688
  - Memory Mapping and Aliasing
    689
- 5 Software
  
  690
- 6 References
  
  691
  - Documents
    691
  - Document Sources
    691
- 7 Technical Support
  
  692
  - Epson LCD/CRT Controllers (S1D13506)
    692
  - NEC Electronics Inc. (V832)
    692
The Strongarm Sa-1110 System Bus/Host Bus Interface Signal Descriptions

695
- 1 Introduction
  
  699
- 2 Interfacing to the Strongarm SA-1110 Bus
  
  700
  - The Strongarm SA-1110 System Bus
    700
    
    Strongarm SA-1110 Overview
    700
    
    Variable-Latency IO Access Overview
    700
    
    Variable-Latency IO Access Cycles
    701
- 3 S1D13506 Host Bus Interface
  
  703
  - Host Bus Interface Pin Mapping
    703
  - Host Bus Interface Signal Descriptions
    704
- 4 Strongarm SA-1110 to S1D13506 Interface
  
  705
  - Hardware Description
    705
  - S1D13506 Hardware Configuration
    706
  - Performance
    706
  - Register/Memory Mapping
    707
  - Strongarm SA-1110 Register Configuration
    708
- 5 Software
  
  709
- 6 References
  
  710
  - Documents
    710
  - Document Sources
    710
- 7 Technical Support
  
  711
  - EPSON LCD/CRT Controllers (S1D13506)
    711
  - Intel Strongarm SA-1110 Micro-Processor
    711

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Epson S1D13506 LCD Controller Manuals

Epson S1D13506 Technical Manual (712 pages)

Table of Contents

Table of Contents

List of Tables

1 Introduction

2 Features

3 Typical System Implementation Diagrams

4 Internal Description

5 Pins

6 C. Characteristics

7 C. Characteristics

8 Registers

Table of Contents

3 Memory Models

4 Look-Up Table (LUT)

5 Virtual Displays

6 Power Save Mode

7 LCD Power Sequencing

8 Hardware Cursor/Ink Layer

9 Swivelview

11 CRT/TV Considerations

12 Mediaplug

13 Identifying the S1D13506

14 Hardware Abstraction Layer (HAL)

15 Sample Code

Table of Contents

Table of Contents

1 Introduction

2 Features

3 Installation and Configuration

4 Technical Description

5 References

6 Parts List

7 Schematic Diagrams

8 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the PC Card Bus

3 S1D13506 Host Bus Interface

4 PC Card to S1D13506 Interface

5 Software

6 References

7 Technical Support

Host Bus Interface Signal Descriptions

1 Introduction

2 Interfacing to the VR4102/VR4111

3 S1D13506 Host Bus Interface

4 VR4102/VR4111 to S1D13506 Interface

5 Software

6 References

7 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the MPC821

3 S1D13506 Host Bus Interface

4 MPC821 to S1D13506 Interface

5 Software

6 References

7 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the PR31500/PR31700

3 S1D13506 Host Bus Interface

4 Direct Connection to the Philips PR31500/PR31700

5 System Design Using the IT8368E PC Card Buffer

6 Software

7 References

8 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the TX3912

3 S1D13506 Host Bus Interface

4 Direct Connection to the Toshiba TX3912

5 System Design Using the IT8368E PC Card Buffer

6 Software

7 References

8 Technical Support

Table of Contents

1 Introduction