Processor Board; Mass Storage Bays - Epson EISA Tower User Manual

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Processor Board

CPU
Cache memory
Math coprocessor

Mass Storage Bays

4865X/25 board: Intel 80486SX, 25 MHz
microprocessor
486/33 board: Intel 80486DX, 33 MHz
microprocessor
Both boards: simulated 8 MHz processor
speed and other processor simulation
speeds selectable through software or
keyboard command
486SX/25 board: 8KB internal cache in the
80486SX microprocessor
486/33 board: 8KB internal cache in the
80486DX microprocessor; 64KB Intel
82485MA-33 Turbocache module with
write-through, two-way set associative
cache memory and controller
486SX/25 board: two sockets available for
optional Weitek WTL4167 and Intel
80487SX math coprocessors
486/33 board: internal coprocessor in the
80486DX chip and one socket for an
optional Weitek WTL4167 coprocessor
Up to six half-height devices maximum;
two half-height or one full-height internal
bays; four half-height or one full-height
and two half-height externally-accessible
bays
Specifications D-3

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