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SCANCLK
T
low
T
high
© National Instruments Corporation
requirements will ensure that SCANCLK is properly transmitted over
TRIG0.
Time low before rising edge
Time high before falling edge
Figure 2-15. SCANCLK Timing Requirements
For output selection time specifications, refer to Appendix A,
Specifications.
Communication Signals
This section describes the methods for communicating on the Serial
Peripheral Interface (SPI) bus and their timing requirements. The
communication signals are SERDATIN, DAQD*/A, SLOT0SEL*,
SERDATOUT, and SERCLK. Furthermore, SS* is produced by Slot 0
according to data acquisition board programming, and SS* timing
relationships will also be discussed. For information on the Slot 0
Slot-Select Register, consult Chapter 4,
The data acquisition board determines to which slot it will talk by writing
a slot-select number to Slot 0. In the case of an SCXI-1001 chassis, this
write also determines to which chassis the data acquisition board will talk.
Writing a slot-select number is also used in programming the Slot 0
hardscan circuitry. Refer to Chapter 5, Programming, for information on
programming the Slot 0 hardscan circuitry.
The following sections detail the procedure for selecting a slot in a
particular chassis. Figure 2-16 illustrates the timing of this procedure with
the example case of selecting Slot 11 in Chassis 9. Notice that the
factory-default chassis address for the SCXI-1000 is address 0. For
information on changing the address of your chassis, consult the SCXI
Chassis User Manual. An SCXI-1000 chassis will respond to any chassis
number.
Chapter 2
T
low
Register
2-41
Configuration and Installation
T
high
400 nsec minimum
250 nsec minimum
Descriptions.
SCXI-1121 User Manual
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