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Chapter 2
Configuration and Installation
Table 2-16. SCXIbus to SCXI-1121 Rear Signal Connector to Data Acquisition Board Pin Equivalences
SCXIbus Line
MOSI
D*/A
INTR*
SPICLK
MISO
SCXI-1121 User Manual
SCXI-1121
Rear Signal
Connector
SERDATIN
DAQD*/A
SLOT0SEL*
SERCLK
EXTSTROBE*
SERDATOUT
The digital timing signals are pins 36 and 43.
•
Pin 36 is used as a clock by the SCXI-1121 to increment the
MUXCOUNTER after each conversion by the data acquisition board
during scanning. This signal is referred to as SCANCLK. Refer to
Chapter 3,
Theory of
•
Pin 43 is a reserved digital input.
The following specifications and ratings apply to the digital I/O lines.
Absolute maximum voltage
Input rating
Digital input specifications (referenced to DIG GND):
V
input logic high voltage
IH
V
input logic low voltage
IL
I
input current leakage
I
Digital output specifications (referenced to DIG GND):
V
output logic high voltage
OH
V
output logic low voltage
OL
Timing Requirements and Communication Protocol
Timing Signal
The data acquisition timing signal is SCANCLK.
SCANCLK is used to increment MUXCOUNTER on its rising edge.
Figure 2-15 shows the timing requirements of the SCANCLK signal. These
Lab-NB/Lab-PC
MIO-16
Lab-PC+/Lab-LC
ADIO0
ADIO1
ADIO2
BDIO0
Operation, for a description of MUXCOUNTER.
5.5 V with respect to DIG GND
2 V minimum
0.8 V maximum
±1 µA maximum
3.7 V minimum at 4 mA maximum
0.4 V maximum at 4 mA maximum
2-40
PC-LPM-16
PB4
DOUT4
PB5
DOUT5
PB6
DOUT6
PB7
DOUT7
PC1
DIN6
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