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Hardscan Control Register (HSCR)
The HSCR contains eight bits that control the setup and operation of the hardscan timing
circuitry of Slot 0. To write to the HSCR, follow the procedure given in the
section of Chapter 5, Programming, using 13 as the slot number, and writing eight bits to the
HSCR. The register will shift in the data present on the MOSI line, bit seven first, when
Slot 13 is selected by the Slot-Select Register.
Type:
Word Size:
Bit Map:
7
6
RSVD
FRT
Bit
7
6
5
4
3
2
© National Instruments Corporation
Write-only
8-bit
5
4
RD
ONCE
Name
Description
RSVD
Reserved.
FRT
Forced Retransmit—This bit, when clear, causes the scan
list in the FIFO to be reinitialized to the first entry, thus
allowing the scan list to be reprogrammed in two steps
instead of having to rewrite the entire list. When this bit is
set, it has no effect.
RD
Read—This bit, when clear, prevents the FIFO from being
read. When set, the FIFO is being read except at the end of
a scan list entry during scanning, when reading is briefly
disabled to advance to the next scan list entry.
ONCE
Once—When set, this bit will cause the Hardscan circuitry
to shut down at the end of the scan list circuitry during a
data acquisition. When clear, the circuitry will wrap
around and continue with the first scan list entry after the
entry is finished.
HSRS*
Hardscan Reset—When clear, this bit causes all the
hardware scanning circuitry, including the FIFO, to be
reset to the power up state. When set, this bit has no effect.
LOAD*
Load—This bit, when clear, forces a loading of the Slot 0
sample counter with the output of the FIFO. When set, this
bit has no effect.
3
2
HSRS*
LOAD*
4-7
Chapter 4
Register Descriptions
Register Writes
1
SCANCONEN
CLKEN
SCXI-1121 User Manual
0
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