Table 3. Post Progress Code Led Example; Table 4. Mrc Progress Codes - Intel P4304XXMFEN2 Service Manual

Intel ® Server Chassis P4304XXMFEN2/P4304XXMUXX Product Family System Integration and Service Guide
MSB
LEDs
LED #7
8h
Status ON
1
Results
Ah
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh
Early POST Memory Initialization MRC Diagnostic Codes
Memory Initialization at the beginning of POST includes multiple functions, including: discovery,
channel training, validation that the DIMM population is acceptable and functional, initialization of the
IMC and other hardware settings, and initialization of applicable RAS configurations.
The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Diagnostic LED Decoder
1 = LED On, 0 = LED Off
Checkpoint Upper Nibble
MSB
8h 4h
LED #7 #6
MRC Progress Codes
B0h 1 0
B1h 1 0
B2h 1 0
B3h 1 0
B4h 1 0
B5h 1 0
B6h 1 0
B7h 1 0
B8h 1 0
B9h 1 0
BAh 1 0
BBh 1 0
BCh 1 0
BFh 1 0
Should a major memory initialization error occur, preventing the system from booting with data
integrity, a beep code is generated, the MRC will display a fatal error code on the diagnostic LEDs, and a
system halt command is executed. Fatal MRC error halts do NOT change the state of the System Status
LED, and they do NOT get logged as SEL events. The following table lists all MRC fatal errors that are
displayed to the Diagnostic LEDs.
Note: Fatal MRC errors will display POST error codes that may be the same as BIOS POST progress
codes displayed later in the POST process. The fatal MRC codes can be distinguished from the BIOS
84

Table 3. POST Progress Code LED Example

Upper Nibble AMBER LEDs
LED #6 LED #5
4h 2h
OFF ON
0 1

Table 4. MRC Progress Codes

Lower Nibble
2h 1h 8h 4h 2h
#5 #4 #3 #2 #1
1 1 0 0 0
1 1 0 0 0
1 1 0 0 1
1 1 0 0 1
1 1 0 1 0
1 1 0 1 0
1 1 0 1 1
1 1 0 1 1
1 1 1 0 0
1 1 1 0 0
1 1 1 0 1
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
LED #4 LED #3
1h 8h
OFF ON
0 1
Ch
LSB
1h
#0
0 Detect DIMM population
1 Set DDR3 frequency
0 Gather remaining SPD data
1 Program registers on the memory controller level
0 Evaluate RAS modes and save rank information
1 Program registers on the channel level
0 Perform the JEDEC defined initialization sequence
1 Train DDR3 ranks
0 Initialize CLTT/OLTT
1 Hardware memory test and init
0 Execute software memory init
1 Program memory map and interleaving
0 Program RAS configuration
1 MRC is done
Lower Nibble GREEN LEDs
LED #2 LED #1
4h 2h
ON OFF
1 0
Description
LSB
LED #0
1h
OFF
0