Texas Instruments SimpleLink MSP432P4 Series Technical Reference Manual

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Msp432P4Xx Simplelink™ Microcontrollers Technical Reference Manual
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MSP432P4xx SimpleLink™ Microcontrollers

Technical Reference Manual

Literature Number: SLAU356I

March 2015 – Revised June 2019

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Summary of Contents for Texas Instruments SimpleLink MSP432P4 Series

Page 1 MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual Literature Number: SLAU356I March 2015 – Revised June 2019...
Page 2: Table Of Contents
System Timer (SysTick) ..............2.2.2 Nested Vectored Interrupt Controller (NVIC) ..................2.2.3 System Control Block (SCB) .................. 2.2.4 Memory Protection Unit (MPU) Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 3 NMI Configuration .................. Watchdog Timer Reset Configuration ....................Peripheral Halt Control ................... Glitch Filtering on Digital I/Os ..................Reset Status and Override Control SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 4 Device Security and Boot Overrides User Considerations ....................Device Descriptor Table ....................5.9.1 TLV Descriptors ....................5.9.2 TLV Checksum ....................5.9.3 Calibration Values Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 5 CSCTL3 Register (offset = 10h) [reset = 0000_00BBh] ..........6.3.6 CSCLKEN Register (offset = 30h) [reset = 0000_000Fh] ............ 6.3.7 CSSTAT Register (offset = 34h) [reset = 0000_0003h] SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 6 ..................8.13.1 DC/DC Error Checking ....................8.14 Entering LPM0 Modes ..................... 8.15 Exiting LPM0 Modes ..................8.16 Entering LPM3 or LPM4 Modes Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 7 9.4.11 FLCTL_PRGBRST_STARTADDR Register (offset = 0058h) ..........9.4.12 FLCTL_PRGBRST_DATA0_0 Register (offset = 060h) ..........9.4.13 FLCTL_PRGBRST_DATA0_1 Register (offset = 064h) ..........9.4.14 FLCTL_PRGBRST_DATA0_2 Register (offset = 068h) SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 8 10.3.3 Advanced Flash Erase ..................10.3.4 Flash Controller Interrupts ................. 10.3.5 Application Benchmarking Features ......... 10.3.6 Support for AM_LF_VCOREx and LPM0_LF_VCOREx Power Modes Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 9 10.4.48 FLCTL_MASSERASE_TIMCTL Register (offset = 011Ch) ..........10.4.49 FLCTL_BURSTPRG_TIMCTL Register (offset = 0120h) ......... 10.4.50 FLCTL_BANK0_MAIN_WEPROT0 Register (offset = 0200h) ......... 10.4.51 FLCTL_BANK0_MAIN_WEPROT1 Register (offset = 0204h) SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 10 11.3.25 DMA_ERRCLR Register (offset = 104Ch) [reset = 0h] ......................... Digital I/O ....................12.1 Digital I/O Introduction ...................... 12.2 Digital I/O Operation ..................12.2.1 Input Registers (PxIN) Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 11 15.2 CRC Checksum Generation .................. 15.2.1 CRC Standard and Bit Order ................... 15.2.2 CRC Implementation ......................15.3 CRC32 Registers ......................AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 12 18.5.12 T32RIS2 Register (offset = 30h) [reset = 0h] ............. 18.5.13 T32MIS2 Register (offset = 34h) [reset = 0h] ............18.5.14 T32BGLOAD2 Register (offset = 38h) [reset = 0h] Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 13 20.3.21 RTCAMIN Register – BCD Format ............20.3.22 RTCAHOUR Register – Hexadecimal Format ..............20.3.23 RTCAHOUR Register – BCD Format ..............20.3.24 RTCADOW Register – Calendar Mode SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 14 22.3.15 ADC14IV Register (offset = 154h) [reset = 00000000h] ..................Comparator E Module (COMP_E) ....................23.1 COMP_E Introduction ...................... 23.2 COMP_E Operation ...................... 23.2.1 Comparator Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 15 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ..................25.2 eUSCI Introduction – SPI Mode ................... 25.3 eUSCI Operation – SPI Mode ................25.3.1 eUSCI Initialization and Reset SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 16 26.4.8 UCBxI2COA0 Register ..................26.4.9 UCBxI2COA1 Register ..................26.4.10 UCBxI2COA2 Register ..................26.4.11 UCBxI2COA3 Register ..................26.4.12 UCBxADDRX Register ................... 26.4.13 UCBxADDMASK Register Contents SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 17 27.3.12 LCDCLRIFG Register 1045 ..................27.3.13 LCDM[index] Register 1046 ..................27.3.14 LCDBM[index] Register 1048 ................... 27.3.15 LCDANM[index] Register 1050 ........................Revision History 1052 SLAU356I – March 2015 – Revised June 2019 Contents Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 18 ......................2-37. IPR7 Register ......................2-38. IPR8 Register ......................2-39. IPR9 Register ......................2-40. IPR10 Register ......................2-41. IPR11 Register List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 19 ......................2-86. DEMCR Register ....................... 2-87. FP_CTRL Register ..................... 2-88. FP_REMAP Register ..................... 2-89. FP_COMP0 Register ..................... 2-90. FP_COMP1 Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 20 ......................2-135. STIM18 Register ......................2-136. STIM19 Register ......................2-137. STIM20 Register ......................2-138. STIM21 Register ......................2-139. STIM22 Register List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 21 ..................4-11. SYS_WDTRESET_CTL Register ..................4-12. SYS_PERIHALT_CTL Register ..................... 4-13. SYS_SRAM_SIZE Register ..................4-14. SYS_SRAM_BANKEN Register ..................4-15. SYS_SRAM_BANKRET Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 22 5-36. SYS_SYSTEM_STAT Register ................... 6-1. Clock System Block Diagram ..................6-2. Module Clock Request System ..................... 6-3. Oscillator Fault Logic List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 23 ................9-11. FLCTL_RDBRST_STARTADDR Register ..................9-12. FLCTL_RDBRST_LEN Register ................9-13. FLCTL_RDBRST_FAILADDR Register .................. 9-14. FLCTL_RDBRST_FAILCNT Register ..................9-15. FLCTL_PRG_CTLSTAT Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 24 10-6. Handling Auto-Verify Error After the Burst Operation ..................10-7. FLCTL_POWER_STAT Register ..................10-8. FLCTL_BANK0_RDCTL Register ..................10-9. FLCTL_BANK1_RDCTL Register List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 25 ................10-54. FLCTL_MASSERASE_TIMCTL Register ................10-55. FLCTL_BURSTPRG_TIMCTL Register ................10-56. FLCTL_BANK0_MAIN_WEPROT0 Register ................10-57. FLCTL_BANK0_MAIN_WEPROT1 Register ................10-58. FLCTL_BANK0_MAIN_WEPROT2 Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 26 ....................11-32. DMA_ALTCLR Register ....................11-33. DMA_PRIOSET Register ....................11-34. DMA_PRIOCLR Register ....................11-35. DMA_ERRCLR Register ......................12-1. PxIV Register List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 27 ......................16-9. CBC Decryption ......................16-10. OFB Encryption ......................16-11. OFB Decryption ......................16-12. CFB Encryption ......................16-13. CFB Decryption SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 28 20-1. RTC_C Block Diagram ..........20-2. RTC_C Offset Error Calibration and Temperature Compensation ....................20-3. RTCCTL0_L Register ....................20-4. RTCCTL0_H Register List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 29 22-12. Precision ADC Grounding and Noise Considerations ....................22-13. ADC14CTL0 Register ....................22-14. ADC14CTL1 Register ...................... 22-15. ADC14LO0 Register ....................... 22-16. ADC14HI0 Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 30 24-23. UCAxIV Register ..................25-1. eUSCI Block Diagram – SPI Mode ..............25-2. eUSCI Master and External Slave (UCSTEM = 0) List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 31 ....................26-27. UCBxI2COA3 Register ....................26-28. UCBxADDRX Register ....................26-29. UCBxADDMASK Register ..................... 26-30. UCBxI2CSA Register ......................26-31. UCBxIE Register SLAU356I – March 2015 – Revised June 2019 List of Figures Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 32 ....................27-26. LCDCLRIFG Register 1045 ....................27-27. LCDM[index] Register 1046 ....................27-28. LCDBM[index] Register 1048 ....................27-29. LCDANM[index] Register 1050 List of Figures SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 33 2-32. ICPR0 Register Field Descriptions ..................2-33. ICPR1 Register Field Descriptions ..................2-34. IABR0 Register Field Descriptions ..................2-35. IABR1 Register Field Descriptions SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 34 2-81. MMFR2 Register Field Descriptions ..................2-82. MMFR3 Register Field Descriptions ..................2-83. ISAR0 Register Field Descriptions ..................2-84. ISAR1 Register Field Descriptions List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 35 2-130. STIM0 Register Field Descriptions ..................2-131. STIM1 Register Field Descriptions ..................2-132. STIM2 Register Field Descriptions ..................2-133. STIM3 Register Field Descriptions SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 36 ..............3-11. RSTCTL_PCMRESET_STAT Register Description ..............3-12. RSTCTL_PCMRESET_CLR Register Description ..............3-13. RSTCTL_PINRESET_STAT Register Description ..............3-14. RSTCTL_PINRESET_CLR Register Description List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 37 ................5-14. SYS_NMI_CTLSTAT Register Description ................ 5-15. SYS_WDTRESET_CTL Register Description ................5-16. SYS_PERIHALT_CTL Register Description ................5-17. SYS_SRAM_SIZE Register Description SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 38 8-4. AM Invalid Transition NMI/interrupt Enable ................8-5. LPM Invalid Transition NMI/Interrupt Enable ..................8-6. PCM Static Clock Request Checks List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 39 ..............9-34. FLCTL_PRGBRST_DATA2_2 Register Description ..............9-35. FLCTL_PRGBRST_DATA2_3 Register Description ..............9-36. FLCTL_PRGBRST_DATA3_0 Register Description ..............9-37. FLCTL_PRGBRST_DATA3_1 Register Description SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 40 ..............10-22. FLCTL_PRGBRST_CTLSTAT Register Description ............10-23. FLCTL_PRGBRST_STARTADDR Register Description ..............10-24. FLCTL_PRGBRST_DATA0_0 Register Description ..............10-25. FLCTL_PRGBRST_DATA0_1 Register Description List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 41 ............10-71. FLCTL_BANK1_MAIN_WEPROT1 Register Description ............10-72. FLCTL_BANK1_MAIN_WEPROT2 Register Description ............10-73. FLCTL_BANK1_MAIN_WEPROT3 Register Description ............10-74. FLCTL_BANK1_MAIN_WEPROT4 Register Description SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 42 ....................12-4. PxIV Register Description ....................12-5. PxIN Register Description .................... 12-6. PxOUT Register Description ..................... 12-7. PxDIR Register Description List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 43 ..................16-13. AESACTL1 Register Description ..................16-14. AESASTAT Register Description ..................16-15. AESAKEY Register Description ..................16-16. AESADIN Register Description SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 44 ..................20-16. RTCDAY Register Description ..................20-17. RTCMON Register Description ..................20-18. RTCMON Register Description ..................20-19. RTCYEAR Register Description List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 45 /Baud Rate BRCLK ............. 24-5. Recommended Settings for Typical Crystals and Baud Rates ................... 24-6. UART State Change Interrupt Flags SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 46 ..................26-14. UCBxI2COA3 Register Description ..................26-15. UCBxADDRX Register Description ................. 26-16. UCBxADDMASK Register Description ..................26-17. UCBxI2CSA Register Description List of Tables SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 47 27-19. LCDCLRIFG Register Description 1045 ..................27-20. LCDM[index] Register Description 1046 .................. 27-21. LCDBM[index] Register Description 1048 ................27-22. LCDANM[index] Register Description 1050 SLAU356I – March 2015 – Revised June 2019 List of Tables Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 48: Preface
Read only bit. Always reads as 0h. A reserved bit. Write only bit. Always reads as 0h. Trademarks SimpleLink, MSP432 are trademarks of Texas Instruments. Arm, Cortex, AMBA are registered trademarks of Arm Limited. All other trademarks are the property of their respective owners.
Page 49: Cortex-M4F Processor
......................Overview ................... Programming Model ....................Memory Model ....................Exception Model ....................Fault Handling .................... Power Management ..................Instruction Set Summary SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 50: Introduction
– Support for up to 64 interrupt sources – Three bits to define the priority of each interrupt (total of eight priority levels) – Dynamic reprioritization of interrupts Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 51: Cortex-M4F Optional Parameters Configuration In Msp432P4Xx
Full debug with data matching. Debug port, Debug support level data matching, Full debug with Data matching AHB-AP, FPB and DWT present SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 52: 1.1.1 Block Diagram
ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. Figure 1-1 shows the CPU block diagram. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 53: Overview
D-code bus Matrix System bus Serial Wire JTAG Debug Debug Port Access Port Copyright © 2016, Texas Instruments Incorporated Figure 1-1. CPU Block Diagram Overview 1.2.1 Bus Interface MSP432P4xx Cortex-M4F implementation contains three high-speed AMBA technology AHB-Lite Bus ® interfaces named ICODE, DCODE, and SBUS (System Bus) and one AMBA technology APB bus named PPB (Private Peripheral Bus).
Page 54: 1.2.2 Integrated Configurable Debug
It also provides conversions between fixed-point and floating- point data formats, and floating-point constant instructions (see Section 2.2.5). Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 55: Programming Model
Privilege Level Stack Used Thread Applications Privileged or unprivileged Main stack or process stack Handler Exception handlers Always privileged Main stack SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 56: 1.3.3 Register Map
Register 7: Cortex General-Purpose Register 7 (R7) Register 8: Cortex General-Purpose Register 8 (R8) Register 9: Cortex General-Purpose Register 9 (R9) Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 57 The PSR IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 58: Psr Register Combinations
On reset, the BASEPRI register is cleared. For more information on exception priority levels, see Section 1.5.2. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 59: 1.3.5 Exceptions And Interrupts
NOTE: For details about the memory map of individual peripherals and valid memory range, see the device-specific data sheet. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 60: 1.4.1 Memory Regions, Types, And Attributes
The memory type and attributes determine the behavior of accesses to the region. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 61: 1.4.2 Memory System Ordering Of Memory Accesses
• The processor has multiple bus interfaces. • Memory or devices in the memory map have different wait states. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 62: 1.4.5 Bit-Banding
A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 63: Sram Memory Bit-Banding Regions
The alias word at 0x2200_001C maps to bit 7 of the bit-band byte at 0x2000_0000: 0x2200.001C = 0x2200_0000+ (0*32) + (7*4) SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 64: 1.4.6 Data Storage
(LSByte) of a word stored at the lowest-numbered byte, and the most-significant byte (MSByte) stored at the highest-numbered byte. Figure 1-4 shows how data is stored. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 65: Exception Model
(and flush the write buffer). Section 2.2.2 for more information on exceptions and interrupts. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 66: 1.5.1 Exception States
Interrupt Control State register (ICSR). • SysTick: A SysTick exception is an exception that the system timer generates when it reaches zero Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 67: 1.5.3 Exception Handlers
• System Handlers: NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 68: 1.5.4 Vector Table
0x0000_0000 to 0x3FFF_FFFF. When configuring the Vector Table Offset Register (VTOR), the offset must be aligned on a 512-byte boundary. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 69: 1.5.5 Exception Priorities
ISR runs only once. Pulse interrupts are mostly used for external signals and for rate or repeat signals. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 70: 1.5.8 Exception Entry And Return
Cortex-M4F stack frame layout when floating- point state is preserved on the stack as the result of an interrupt or an exception. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 71: Exception Stack Frame
If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 72: Fault Handling
Attempting to execute an instruction from a memory region marked as Non-Executable (XN). • An MPU fault because of a privilege violation or an attempt to access an unmanaged region. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 73: 1.6.1 Fault Types
An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. • A fault occurs and the handler for that fault is not enabled. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 74: 1.6.3 Fault Status Registers And Fault Address Registers
NOTE: For details on the mechanisms of entry to and exit from various low-power modes, see the Power Control Manager (PCM) chapter. Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 75: Instruction Set Summary
Load Register with byte – LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes – LDREX Rt, [Rn, #offset] Load Register Exclusive – SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 76 Rd, Rn, #lsb, #width Signed Bit Field Extract – SDIV {Rd,} Rn, Rm Signed Divide – {Rd,} Rn, Rm Select bytes – Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 77 Dual extend 8 bits to 16 and add – SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 78 Sd, <Sm | #0.0> FPSCR point register and zero with Invalid Operation check VCVT.S32.F32 Sd, Sm Convert between floating-point and integer – Cortex-M4F Processor SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 79 Stores an extension register to memory – VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract – – Wait For Event – – Wait For Interrupt – SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Processor Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 80: Cortex-M4F Peripherals
Page ..............Cortex-M4F Peripherals Introduction ..............Functional Peripherals Description ................Debug Peripherals Description ................. Functional Peripherals Registers ................Debug Peripherals Registers Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 81: Cortex-M4F Peripherals Introduction
An internal clock source control based on missing/meeting durations. The COUNT bit in the STCSR control and status register can be used to determine if an action completed within a set duration, as SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 82: Nested Vectored Interrupt Controller (Nvic)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 83: System Control Block (Scb)
The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. See Section 2.4.5 for bit description of System Control Block registers. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 84: Memory Protection Unit (Mpu)
The RASR register can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 85: Tex, S, C, And B Bit Field Encoding
Table 2-4. AP Bit Field Encoding Privileged Unprivileged AP Bit Field Description Permissions Permissions No access No access All accesses generate a permission fault. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 86: Memory Region Attributes For Msp432P4Xx Devices
; R3 = attributes ; R4 = address LDR R0,=RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 87 Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 88: Srd Use Example
• Sixteen 64-bit double-word registers, D0-D15 • Thirty-two 32-bit single-word registers, S0-S31 • A combination of registers from the above views Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 89: Fpu Register Bank
754-2008 standard. Unsupported operations include, but are not limited to the following: • Remainder • Round floating-point number to integer-valued floating-point number • Binary-to-decimal conversions SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 90: Qnan And Snan Handling
UFC flag, FPSCR[3], is set. See the Arm Architecture Reference Manual for information on flush-to-zero mode. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 91 A PC sampler event trigger • A data address sampler event trigger. The DWT contains counters for: • Clock cycles (CYCCNT) SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 92: Tpiu Block Diagram
TPIU Components • Asynchronous FIFO: The asynchronous FIFO enables trace data to be driven out at a speed that is not Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 93: 2.4.1 Fpu Registers
Media and FP Feature Register 0 (MVFR0) read-only 10110021h Section 2.4.1.4 F44h MVFR1 Media and FP Feature Register 1 (MVFR1) read-only 11000011h Section 2.4.1.5 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 94: Fpccr Register
Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame. LSPACT Indicates whether Lazy preservation of the FP state is active. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 95: Fpcar Register
RESERVED 30-2 ADDRESS Holds the (double-word-aligned) location of the unpopulated floating- point register space allocated on an exception stack frame. RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 96: Fpdscr Register
Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions). 21-0 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 97: Mvfr0 Register
Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 98: Mvfr1 Register
Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 99: 2.4.2 Mpu Registers
MPU Alias 3 Region Base Address register read-write 00000000h Section 2.4.2.10 DB8h RASR_A3 MPU Alias 3 Region Attribute and Size register read-write 00000000h Section 2.4.2.11 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 100: Type Register
MPU indicating eight MPU regions, otherwise it contains 0x00. RESERVED SEPARATE Because the processor core uses only a unified MPU, SEPARATE is always 0. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 101: Ctrl Register
Reset clears the HFNMIENA bit. ENABLE MPU enable bit. Reset clears the ENABLE bit. 0b = disable MPU 1b = enable MPU SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 102: Rnr Register
Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 103: Rbar Register
0b = MPU Region Number Register remains unchanged and is interpreted. 1b = MPU Region Number Register is overwritten by bits 3:0 (the REGION value). REGION MPU region override field. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 104: Rasr Register
Type extension field Shareable bit 0b = not shareable 1b = shareable Cacheable bit 0b = not cacheable 1b = cacheable Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 105 11010b = 128MB 11011b = 256MB 11100b = 512MB 11101b = 1GB 11110b = 2GB 11111b = 4GB ENABLE Region enable bit. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 106: Rbar_A1 Register
0b = MPU Region Number Register remains unchanged and is interpreted. 1b = MPU Region Number Register is overwritten by bits 3:0 (the REGION value). REGION MPU region override field. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 107: Rasr_A1 Register
1b = shareable Cacheable bit 0b = not cacheable 1b = cacheable Bufferable bit 0b = not bufferable 1b = bufferable SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 108: Rasr_A1 Register Field Descriptions
11010b = 128MB 11011b = 256MB 11100b = 512MB 11101b = 1GB 11110b = 2GB 11111b = 4GB ENABLE Region enable bit. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 109: Rbar_A2 Register
0b = MPU Region Number Register remains unchanged and is interpreted. 1b = MPU Region Number Register is overwritten by bits 3:0 (the REGION value). REGION MPU region override field. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 110: Rasr_A2 Register
1b = shareable Cacheable bit 0b = not cacheable 1b = cacheable Bufferable bit 0b = not bufferable 1b = bufferable Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 111: Rasr_A2 Register Field Descriptions
11010b = 128MB 11011b = 256MB 11100b = 512MB 11101b = 1GB 11110b = 2GB 11111b = 4GB ENABLE Region enable bit. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 112: Rbar_A3 Register
0b = MPU Region Number Register remains unchanged and is interpreted. 1b = MPU Region Number Register is overwritten by bits 3:0 (the REGION value). REGION MPU region override field. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 113: Rasr_A3 Register
1b = shareable Cacheable bit 0b = not cacheable 1b = cacheable Bufferable bit 0b = not bufferable 1b = bufferable SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 114: Rasr_A3 Register Field Descriptions
11010b = 128MB 11011b = 256MB 11100b = 512MB 11101b = 1GB 11110b = 2GB 11111b = 4GB ENABLE Region enable bit. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 115: 2.4.3 Nvic Registers
IPR15 Irq 60 to 63 Priority Register read-write 00000000h Section 2.4.3.26 F00h STIR Software Trigger Interrupt Register write-only 00000000h Section 2.4.3.27 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 116: Iser0 Register
Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 117: Icer0 Register
Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 118: Ispr0 Register
Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 119: Icpr0 Register
Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 120: Iabr0 Register
Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 121: Ipr0 Register
PRI_6 Priority of interrupt 6 16-20 RESERVED 15-13 PRI_5 Priority of interrupt 5 8-12 RESERVED PRI_4 Priority of interrupt 4 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 122: Ipr2 Register
PRI_14 Priority of interrupt 14 16-20 RESERVED 15-13 PRI_13 Priority of interrupt 13 8-12 RESERVED PRI_12 Priority of interrupt 12 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 123: Ipr4 Register
PRI_22 Priority of interrupt 22 16-20 RESERVED 15-13 PRI_21 Priority of interrupt 21 8-12 RESERVED PRI_20 Priority of interrupt 20 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 124: Ipr6 Register
PRI_30 Priority of interrupt 30 16-20 RESERVED 15-13 PRI_29 Priority of interrupt 29 8-12 RESERVED PRI_28 Priority of interrupt 28 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 125: Ipr8 Register
PRI_38 Priority of interrupt 38 16-20 RESERVED 15-13 PRI_37 Priority of interrupt 37 8-12 RESERVED PRI_36 Priority of interrupt 36 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 126: Ipr10 Register
PRI_46 Priority of interrupt 46 16-20 RESERVED 15-13 PRI_45 Priority of interrupt 45 8-12 RESERVED PRI_44 Priority of interrupt 44 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 127: Ipr12 Register
PRI_54 Priority of interrupt 54 16-20 RESERVED 15-13 PRI_53 Priority of interrupt 53 8-12 RESERVED PRI_52 Priority of interrupt 52 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 128: Ipr14 Register
PRI_62 Priority of interrupt 62 16-20 RESERVED 15-13 PRI_61 Priority of interrupt 61 8-12 RESERVED PRI_60 Priority of interrupt 60 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 129: Stir Register
Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 130: 2.4.4 Systick Registers
Undefined Section 2.4.4.2 STCVR SysTick Current Value Register read-write Undefined Section 2.4.4.3 STCR SysTick Calibration Value Register read-only Undefined Section 2.4.4.4 Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 131: Stcsr Register
CLKSOURCE Clock source. 0b = Not applicable 1b = Core clock TICKINT ENABLE Enable SysTick counter 0b (R/W) = Counter disabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 132: Strvr Register
Description 31-24 RESERVED Undefined 23-0 RELOAD Undefined Value to load into the SysTick Current Value Register when the counter reaches 0. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 133: Stcvr Register
0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 134: Stcr Register
This could affect its suitability as a software real time clock. 29-24 RESERVED Undefined 23-0 TENMS Undefined Reads as zero. Indicates calibration value is not known. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 135: Bus
Section 2.4.5.28 D70h ISAR4 ISA Feature register4 read-only 01310132h Section 2.4.5.29 D88h CPACR Coprocessor Access Control Register read-write 00F00000h Section 2.4.5.30 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 136: Cpuid Register
Implementation defined variant number. 19-16 CONSTANT Reads as 0xC 15-4 PARTNO C24h Number of processor within family. REVISION Implementation defined revision number. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 137: Icsr Register
ISRPENDING Interrupt pending flag. Excludes NMI and faults. 0b (R/W) = interrupt not pending 1b (R/W) = interrupt pending 21-18 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 138 This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set. 10-9 RESERVED VECTACTIVE Active ISR number field. Reset clears the VECTACTIVE field. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 139: Vtor Register
Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space. RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 140: Aircr Register
So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 141 The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 142: Scr Register
0b (R/W) = do not sleep when returning to thread mode 1b (R/W) = sleep on ISR exit RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 143: Ccr Register
When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 144: Shpr1 Register
Priority of system handler 7. 23-16 PRI_6 Priority of system handler 6. 15-8 PRI_5 Priority of system handler 5. PRI_4 Priority of system handler 4. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 145: Shpr2 Register
Priority of system handler 11. 23-16 PRI_10 Priority of system handler 10. 15-8 PRI_9 Priority of system handler 9. PRI_8 Priority of system handler 8. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 146: Shpr3 Register
Priority of system handler 15. 23-16 PRI_14 Priority of system handler 14. 15-8 PRI_13 Priority of system handler 13. PRI_12 Priority of system handler 12. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 147: Shcsr Register
0b (R/W) = not pended 1b (R/W) = pended SYSTICKACT SysTick active flag. 0b (R/W) = not active 1b (R/W) = active SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 148 0b (R/W) = not active 1b (R/W) = active MEMFAULTACT MemManage active flag. 0b (R/W) = not active 1b (R/W) = active Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 149: Cfsr Register
Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 150 This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 151: Hfsr Register
This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 152: Dfsr Register
Halt request flag. The processor is halted on the next instruction. 0b (R/W) = no halt request 1b (R/W) = halt requested by NVIC, including step Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 153: Mmfar Register
Flags in the Memory Manage Fault Status Register indicate the cause of the fault SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 154: Bfar Register
Flags in the Bus Fault Status Register indicate the cause of the fault Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 155: Afsr Register
Table 2-74. AFSR Register Field Descriptions Field Type Reset Description 31-0 IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 156: Pfr0 Register
11b (R/W) = Thumb-2 encoding with all Thumb-2 basic instructions STATE0 State0 (T-bit == 0) 0b (R/W) = no ARM encoding 1b (R/W) = N/A Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 157: Pfr1 Register
Reset Description 31-12 RESERVED 11-8 MICROCONTROLLER_P Microcontroller programmer's model ROGRAMMERS_MODEL 0b (R/W) = not supported 10b (R/W) = two-stack support RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 158: Dfr0 Register
Microcontroller Debug Model - memory mapped EBUG_MODEL 0b (R/W) = not supported 1b (R/W) = Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) 19-0 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 159: Afr0 Register
Figure 2-70. AFR0 Register RESERVED RESERVED RESERVED RESERVED Table 2-78. AFR0 Register Field Descriptions Field Type Reset Description 31-0 RESERVED RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 160: Mmfr0 Register
1b (R/W) = IMPLEMENTATION DEFINED (N/A) 10b (R/W) = PMSA base (features as defined for ARMv6) (N/A) 11b (R/W) = PMSAv7 (base plus subregion support) RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 161: Mmfr1 Register
Figure 2-72. MMFR1 Register RESERVED RESERVED RESERVED RESERVED Table 2-80. MMFR1 Register Field Descriptions Field Type Reset Description 31-0 RESERVED RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 162: Mmfr2 Register
27-24 WAIT_FOR_INTERRUPT wait for interrupt stalling _STALLING 0b (R/W) = not supported 1b (R/W) = wait for interrupt supported 23-0 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 163: Mmfr3 Register
Figure 2-74. MMFR3 Register RESERVED RESERVED RESERVED RESERVED Table 2-82. MMFR3 Register Field Descriptions Field Type Reset Description 31-0 RESERVED RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 164: Isar0 Register
1b (R/W) = adds BFC, BFI, SBFX, UBFX BITCOUNT_INSTRS BitCount instructions 0b (R/W) = no bit-counting instructions present 1b (R/W) = adds CLZ RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 165: Isar1 Register
0b (R/W) = no scalar (i.e. non-SIMD) sign/zero-extend instructions present 1b (R/W) = adds SXTB, SXTH, UXTB, UXTH 10b (R/W) = N/A 11-0 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 166: Isar2 Register
11b (R/W) = adds PLI LOADSTORE_INSTRS LoadStore instructions 0b (R/W) = no additional normal load/store instructions present 1b (R/W) = adds LDRD/STRD Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 167: Isar3 Register
1b (R/W) = adds SSAT, USAT (and the Q flag in the PSRs) 11b (R/W) = N/A SATRUATE_INSTRS Saturate instructions 0b (R/W) = no non-SIMD saturate instructions present 1b (R/W) = N/A SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 168: Isar4 Register
00b (R/W) = no "T variant" instructions exist 01b (R/W) = adds LDRBT, LDRT, STRBT, STRT 10b (R/W) = adds LDRHT, LDRSBT, LDRSHT, STRHT Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 169: Cpacr Register
11b = Full access Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor. 19-0 RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 170: 2.4.6 Scnscb Registers
Register Name Type Reset Section ICTR Interrupt Control Type Register read-only 00000001h Section 2.4.6.1 ACTLR Auxiliary Control Register read-write 00000000h Section 2.4.6.2 Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 171: Ictr Register
0011b = 97 to 128 0100b = 129 to 160 0101b = 161 to 192 0110b = 193 to 224 0111b = 225 to 256 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 172: Actlr Register
DISMCYCINT Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor because LDM/STM completes before interrupt stacking occurs. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 173: Coredebug Registers
Debug Core Register Data Register read-write Undefined Section 2.4.7.3 DFCh DEMCR Debug Exception and Monitor Control Register read-write 00000000h Section 2.4.7.4 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 174: Dhcsr Register
The core is in debug state when S_HALT is set. S_REGRDY Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. 15-6 RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 175 It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 176: Dcrsr Register
10010b (R/W) = PSP (Process SP) 10100b (R/W) = CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0] Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 177: Dcrdr Register
Table 2-95. DCRDR Register Field Descriptions Field Type Reset Description 31-0 DBGTMP Undefined Data temporary cache, for reading and writing registers SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 178: Demcr Register
POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 179 CAR register. VC_MMERR Debug trap on Memory Management faults. RESERVED VC_CORERESET Reset Vector Catch. Halt running system if Core reset occurs. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 180: 2.5.1 Fpb Registers
00000000h Section 2.5.1.8 FP_COMP6 Flash Patch Comparator Registers read-write 00000000h Section 2.5.1.9 FP_COMP7 Flash Patch Comparator Registers read-write 00000000h Section 2.5.1.10 Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 181: Fp_Ctrl Register
1 to this write-only bit. ENABLE Flash patch unit enable bit 0b (R/W) = flash patch unit disabled 1b (R/W) = flash patch unit enabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 182: Fp_Remap Register
Table 2-99. FP_REMAP Register Field Descriptions Field Type Reset Description 31-29 RESERVED 28-5 REMAP Remap base address field. RESERVED Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 183: Fp_Comp0 Register
0b (R/W) = Flash Patch Comparator Register 0 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 0 compare and remap enabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 184: Fp_Comp1 Register
0b (R/W) = Flash Patch Comparator Register 1 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 1 compare and remap enabled Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 185: Fp_Comp2 Register
0b (R/W) = Flash Patch Comparator Register 2 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 2 compare and remap enabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 186: Fp_Comp3 Register
0b (R/W) = Flash Patch Comparator Register 3 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 3 compare and remap enabled Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 187: Fp_Comp4 Register
0b (R/W) = Flash Patch Comparator Register 4 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 4 compare and remap enabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 188: Fp_Comp5 Register
0b (R/W) = Flash Patch Comparator Register 5 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 5 compare and remap enabled Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 189: Fp_Comp6 Register
0b (R/W) = Flash Patch Comparator Register 6 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 6 compare and remap enabled SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 190: Fp_Comp7 Register
0b (R/W) = Flash Patch Comparator Register 7 compare and remap disabled 1b (R/W) = Flash Patch Comparator Register 7 compare and remap enabled Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 191: Cyccnt Register
Undefined Section 2.5.2.18 MASK3 DWT Mask Register 3 read-write Undefined Section 2.5.2.19 FUNCTION3 DWT Function Register 3 read-write 00000000h Section 2.5.2.20 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 192: Ctrl Register
(every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit. 0b (R/W) = Sleep count events disabled. 1b (R/W) = Sleep count events enabled. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 193 PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 194: Cyccnt Register Field Descriptions
CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 195: Cpicnt Register
If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 196: Exccnt Register
An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 197: Sleepcnt Register
FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 198: Lsucnt Register
LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 199: Foldcnt Register
Reset Description 31-8 RESERVED Undefined FOLDCNT Undefined This counts the total number folded instructions. This counter initializes to 0 when enabled. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 200: Pcsr Register
Table 2-116. PCSR Register Field Descriptions Field Type Reset Description 31-0 EIASAMPLE Undefined Execution instruction address sample, or 0xFFFFFFFF if the core is halted. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 201: Comp0 Register
Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT). SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 202: Mask0 Register
So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 203: Function0 Register
Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 204 1111b (R/W) = EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 205: Comp1 Register
Field Type Reset Description 31-0 COMP Undefined Data value to compare against PC and the data address as given by DWT_FUNCTION1. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 206: Mask1 Register
So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 207: Function1 Register
CYCMATCH Only available in comparator 0. When set, this comparator compares against the clock cycle counter. RESERVED SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 208 1111b (R/W) = EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 209: Comp2 Register
Field Type Reset Description 31-0 COMP Undefined Data value to compare against PC and the data address as given by DWT_FUNCTION2. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 210: Mask2 Register
So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 211: Function2 Register
Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 212 1111b (R/W) = EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 213: Comp3 Register
Field Type Reset Description 31-0 COMP Undefined Data value to compare against PC and the data address as given by DWT_FUNCTION3. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 214: Mask3 Register
So, if COMP is 3, this matches a word access of 0, because 3 would be within the word. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 215: Function3 Register
Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 216 1111b (R/W) = EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 217: 2.5.3 Itm Registers
00000000h Section 2.5.3.37 FB0h ITM Lock Access Register write-only 00000000h Section 2.5.3.38 FB4h ITM Lock Status Register read-only 00000003h Section 2.5.3.39 SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 218: Stim0 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 219: Stim1 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 220: Stim2 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 221: Stim3 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 222: Stim4 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 223: Stim5 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 224: Stim6 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 225: Stim7 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 226: Stim8 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 227: Stim9 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 228: Stim10 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 229: Stim11 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 230: Stim12 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 231: Stim13 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 232: Stim14 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 233: Stim15 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 234: Stim16 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 235: Stim17 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 236: Stim18 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 237: Stim19 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 238: Stim20 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 239: Stim21 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 240: Stim22 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 241: Stim23 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 242: Stim24 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 243: Stim25 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 244: Stim26 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 245: Stim27 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 246: Stim28 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 247: Stim29 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 248: Stim30 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 249: Stim31 Register
1 = Stimulus Port FIFO can accept at least one word 0 = Stimulus Port FIFO full or when Stimulus Port is disabled by the Trace Enable Register SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 250: Ter Register
Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24]. Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 251: Tcr Register
Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 252: Iwr Register
RESERVED R/W-0h RESERVED R/W-0h RESERVED INTEGRATION R/W-0h R/W-0h Table 2-166. IMCR Register Field Descriptions Field Type Reset Description 31-1 RESERVED INTEGRATION Cortex-M4F Peripherals SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 253: Lar Register
Write access to component is blocked. All writes are ignored, reads are permitted. PRESENT Indicates that a lock mechanism exists for this component. SLAU356I – March 2015 – Revised June 2019 Cortex-M4F Peripherals Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 254 This chapter describes the Reset Controller in MSP432P4xx devices..........................Topic Page ..................... Introduction ..................Reset Classification .................... RSTCTL Registers Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 255: Reset Classes
A user-driven full chip reset. This reset can be initiated either through the RSTn pin, through the debugger, through the SYSCTL. • DCO short-circuit fault in external resistor mode of operation. SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 256 Refer to device specific datasheet for details on the available Hard Reset sources. NOTE: A Hard Reset is activated whenever a reset that is higher in class is active. Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 257 Alternatively, the SYSRESETREQ bit of the same register can be used to generate a Hard Reset on the device. SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 258: Rstctl Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 259: Rstctl_Reset_Req Register
If written with 1, generates a Hard Reset request to the Reset Controller SOFT_REQ If written with 1, generates a Soft Reset request to the Reset Controller SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 260: Rstctl_Hardreset_Stat Register
Refer to the device-specific data sheet for the mapping of device-level Hard Reset sources to the appropriate bit in this register. Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 261: Rstctl_Hardreset_Clr Register
Write 0 has no effect. SRC0 Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT. Write 0 has no effect. SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 262: Rstctl_Hardreset_Set Register
SRC0 Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and initiates a Hard Reset). Write 0 has no effect. Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 263: Rstctl_Softreset_Stat Register
Refer to the device-specific data sheet for the mapping of device-level Soft Reset sources to the appropriate bit in this register. SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 264: Rstctl_Softreset_Clr Register
Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT. Write 0 has no effect. SRC0 Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT. Write 0 has no effect. Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 265: Rstctl_Softreset_Set Register
SRC0 Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and initiates a Soft Reset). Write 0 has no effect. SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 266: Rstctl_Pssreset_Stat Register
Field Type Reset Description 31-1 Reserved Reserved. Always reads 0h Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 267: Rstctl_Pcmreset_Stat Register
Field Type Reset Description 31-1 Reserved Reserved. Always reads 0h Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 268: Rstctl_Pinreset_Stat Register
Field Type Reset Description 31-1 Reserved Reserved. Always reads 0h Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 269: Rstctl_Rebootreset_Stat Register
Table 3-16. RSTCTL_REBOOTRESET_CLR Register Description Field Type Reset Description 31-1 Reserved Reserved. Always reads 0h Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT SLAU356I – March 2015 – Revised June 2019 Reset Controller (RSTCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 270: Rstctl_Csreset_Stat Register
Reserved. Always reads 0h. Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as DCOR_SHTIFG flag in CSIFG register of clock system Reset Controller (RSTCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 271 ....................Device Security ..................Device Descriptor Table ..........4.10 Arm Cortex-M4F ROM Table Based Part Number .................... 4.11 SYSCTL Registers SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 272: Sysctl Introduction
SRAM banks are ready for read or write operations. This is handled transparently and does not require any code intervention. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 273: Nmi Configuration
I/Os are bypassed. The glitch filter is automatically bypassed on a digital I/O when it is configured for peripheral or analog functionality by programming the respective PySEL0.x and PySEL1.x registers. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 274: Reset Status And Override Control
All debugger (JTAG or SWD) or bootloader (BSL) accesses to secure memory zones are treated as unauthorized and also return an error response. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 275: Ip Protected Secure Zones Representation
The device has IP protection enabled, and the CPU is currently executing in one of the defined secure memory zones SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 276 Firmware or data load to a JTAG and SWD locked device is done by invoking the BSL. The update could be either of the two following categories: 1. Unencrypted update 2. Encrypted update System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 277: Data Setup For Encrypted Update
The update could be any of the two following categories: 1. Unencrypted update 2. Encrypted update SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 278: Data Setup For Ip Protected Secure Zone Unencrypted Update
The following are the main uses of boot-overrides: • Setting up device JTAG and SWD lock. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 279: Boot Override Flow
SYS_BOOTOVER_REQ0 register and proceeds to execute the required command. Figure 4-5 provides the flow-chart for invoking factory reset boot override command through JTAG. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 280: Factory Reset Boot Override Command Through Jtag
SYS_BOOTOVER_ACK register and SYS_BOOTOVER_ACK register and Clear SYS_BOOTOVER_REQ0/1 Clear SYS_BOOTOVER_REQ0/1 registers. registers. Reboot Figure 4-5. Factory Reset Boot Override Command Through JTAG System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 281: Boot Override Flash Mailbox
JTAG and SWD lock unencrypted password 0x44-0x50 JTAG_SWD_LOCK_UNENC_PWD[0-3] 0xFFFFFFFF when security is disabled. 0x54 Acknowledgment for this command 0x58-0x5C Reserved Reserved SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 282: Boot Override Flash Mailbox
Disable = 0xFFFFFFFF(default state) 0x110 SEC_ZONE1_DATA_EN Enable = 0x00000000 (any value other than 0xFFFFFFFF) 0x114 Acknowledgment for this command 0x118- RESERVED 0xFFFFFFFF 0x11C System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 283 Disable = 0xFFFFFFFF (default state) 0x1D0 SEC_ZONE3_DATA_EN Enable = 0x00000000 (any value other than 0xFFFFFFFF) 0x1D4 Acknowledgment for this command 0x1D8- RESERVED 0xFFFFFFFF 0x1DC SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 284 User cannot initiate a partial update to the IP protected secure zone. 0x214 Acknowledgment for this command 0x218 Reserved 0xFFFFFFFF System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 285 Table 4-1 shows the different CMD and ACK values to be provided by the application to invoke a boot- override. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 286: Commands Used By Boot-Code For Boot Override
ERROR (JTAG based command) 0xDEAD0000 ERROR (Mailbox based command) 0x0000DEAD DEFAULT 0xFFFFFFFF The following is an example of boot-over ride setting. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 287 IP protection and JTAG and SWD lock, if the boot-override ACK field has a value of 0xACE. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 288 4KB (flash sector size). Users should also ensure that the start address of the encrypted update is a 4KB aligned address. 8. When Factory Reset is disabled, it cannot be enabled again. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 289: Device Descriptor Table
Len N Final TLV entry Value field N (optional) TLV End Word TLV end word Figure 4-6. Device Descriptor Table SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 290: Tag Values
= (sum1 >> 16) + (sum1 & 0xFFFF); sum2 += sum1; sum2 = (sum2 >> 16) + (sum2 & 0xFFFF); return (sum2<<16) | sum1; System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 291: Clock System Calibration Data
DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 Word DCO ER mode: DCO Constant (K) for DCORSEL 5 SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 292: Adc Calibration Data
The temperature (Temp, °C) can be computed as follows for each of the reference voltages used in the ADC measurement: System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 293: Flash Information Descriptor
BSL Configuration Word Port Interface Configuration for UART Word Port Interface Configuration for SPI Word Port Interface Configuration for I SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 294: Arm Cortex-M4 Peripheral Id Register Description
As an example, the ROM table with IEEE 1149.1-complaint device IDCODE for the MSP432P401xx MCU is 0000-1011-1001-1010-1111-0000-0010-1111 (see Figure 4-8). Figure 4-8. Example of ROM PID Entries for MSP432P401xx MCU System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 295: 4.11 Sysctl Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 296: Sys_Reboot_Ctl Register Description
Key to enable writes to bit 0. Bit 0 is written only if WKEY is 69h in the same write cycle. Reserved Reserved. Reads return 0h REBOOT Write 1 initiates a Reboot of the device System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 297: Sys_Nmi_Ctlstat Register
When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 298: Sys_Wdtreset_Ctl Register
1b = WDT password violation event generates Hard reset TIMEOUT 0b = WDT timeout event generates Soft reset 1b = WDT timeout event generates Hard reset System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 299: Sys_Perihalt_Ctl Register
1b = freezes peripheral operation when CPU is halted HALT_T16_0 0b = peripheral operation unaffected when CPU is halted 1b = freezes peripheral operation when CPU is halted SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 300: Sys_Sram_Size Register Description
Indicates the size of SRAM on the device. See the device-specific data sheet for the amount of SRAM available for the device. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 301: Sys_Sram_Banken Register
Writes to this bit are allowed ONLY when the BNK_RDY bit in SYS_SRAM_STAT is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready, and writes to this bit are ignored. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 302: Sys_Sram_Bankret Register
Writes to this bit are allowed ONLY when the SRAM_RDY bit of this register is set to 1. If the SRAM_RDY bit is 0, writes to this bit are ignored. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 303: Sys_Flash_Size Register
Indicates the size of the Flash main memory on the device. See the device-specific data sheet for the size of flash main memory. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 304: Sys_Dio_Gltflt_Ctl Register Description
Reserved. Always reads 0h GLTCH_EN 0b = Disables glitch filter on the digital I/Os 1b = Enables glitch filter on the digital I/Os System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 305: Sys_Secdata_Unlock Register Description
Write to unlock : 0x695A (only unlocks the same IP protected secure zone as that of the code writing to this register) Other writes : Lock SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 306: Sys_Master_Unlock Register
1000h are enabled or locked Read back : 0xA596 when unlocked, 0x0 when locked Write to unlock : 0x695A Other writes : Lock System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 307: Sys_Bootover_Req0 Register
Table 4-23. SYS_BOOTOVER_REQ0 Register Description Field Type Reset Description 31-0 REGVAL Value set by debugger, read and clear by the CPU SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 308: Sys_Bootover_Req1 Register
Type Reset Description 31-0 REGVAL Value is set by the debugger, and it is read and cleared by the CPU. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 309: Sys_Bootover_Ack Register Description
Table 4-25. SYS_BOOTOVER_ACK Register Description Field Type Reset Description 31-0 REGVAL Value set by CPU, read/clear by the debugger SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 310: Sys_Reset_Req Register Description
When written with 1, generates a Reboot Reset pulse to the device Reset Controller undefine When written with 1, generates a POR pulse to the device Reset Controller System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 311: Sys_Reset_Statover Register
Therefore, the application must program the hard and soft reset bits to override both the resets. The status of resets are still reflected in the system registers even when the reset overrides have been programmed. SLAU356I – March 2015 – Revised June 2019 System Controller (SYSCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 312: Sys_System_Stat Register
Indicates if JTAG and SWD Lock is active DBG_SEC_ACT undefine Indicates if the Debug Security is currently active Reserved undefine Reserved. System Controller (SYSCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 313 Device Security ..................Device Descriptor Table ..........5.10 Arm Cortex-M4F ROM Table Based Part Number ..................5.11 SYSCTL_A Registers SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 314: Example Bank And Block Organization Of Sram
Block 1 (8KB) 64KB per bank Block 31 Block 7 (8KB) Figure 5-1. Example Bank and Block Organization of SRAM System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 315 The watchdog timer module can be configured to source a hard reset or soft reset in the SYS_WDTRESET_CTL register. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 316 Access into a completely locked device can be enabled again by a factory reset boot override request through the SYSCTL_A registers and the flash boot-override mailbox. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 317: Ip Protected Secure Zones Representation
Disabling the debugger connection whenever execution is inside a secure zone can help making attacks against an IP Protected Secure Zone harder. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 318 When a secure zone is unlocked for data, data accesses to that zone is still permitted only for code executing from within the same zone. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 319 7. The status of the update is indicated in the ACK field of the specific command in the boot-override mailbox. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 320: Data Setup For Encrypted Update
PAYLOAD PASSWORD Figure 5-4. Data Setup for IP Protected Secure Zone Unencrypted Update System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 321 JTAG and SWD • The flash mailbox Figure 5-5 shows the general boot-override flow for the JTAG flash mailbox. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 322: Boot Override Flow
Figure 5-6 shows the flow chart for invoking the factory reset boot override command through JTAG. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 323: Factory Reset Boot Override Command Through Jtag
SYS_BOOTOVER_ACK register and Clear SYS_BOOTOVER_REQ0/1 Clear SYS_BOOTOVER_REQ0/1 registers. registers. Reboot Figure 5-6. Factory Reset boot override command through JTAG SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 324 JTAG and SWD lock unencrypted password 0x44-0x50 JTAG_SWD_LOCK_UNENC_PWD[0-3] 0xFFFFFFFF when security is disabled. 0x54 Acknowledgment for this command 0x58-0x5C Reserved Reserved System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 325 0x110 SEC_ZONE1_DATA_EN Enable = 0x00000000 (Any value other than 0xFFFFFFFF) 0x114 Acknowledgment for this command 0x118- RESERVED 0xFFFFFFFF 0x11C SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 326 0x1D0 SEC_ZONE3_DATA_EN Enable = 0x00000000 (Any value other than 0xFFFFFFFF) 0x1D4 Acknowledgment for this command 0x1D8- RESERVED 0xFFFFFFFF 0x1DC System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 327 User cannot initiate a partial update to the IP protected secure zone. 0x214 Acknowledgment for this command 0x218 Reserved 0xFFFFFFFF SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 328 NOTE: The default value of FACTORY_RESET_ENABLE is 0xFFFFFFFF which is opposite than the "Enable" setting for all other applicable parameters in the boot override mailbox. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 329: Boot Override Parameters Restrictions
JTAG_SWD_LOCK_SECEN and SEC_ZONE1_EN then the ANY_CONFIG Command to provide is: 0x00080000 | 0x00200000 = 0x00280000 NONE 0x00000000; 0xFFFFFFFF SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 330: Acks Used By Boot-Code To Indicate Status Of Boot Override
If the boot-override ACK field has a value of 0xACE, the device is secured with IP protection. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 331 Table 5-2. h. After factory reset is disabled, it cannot be enabled again. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 332: Device Descriptor Table
The length field is one 32-bit word and represents the length of the descriptor in words. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 333: Tag Values
= (sum1 >> 16) + (sum1 & 0xFFFF); sum2 += sum1; sum2 = (sum2 >> 16) + (sum2 & 0xFFFF); return (sum2<<16) | sum1; SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 334: Clock System Calibration Data
DCO ER mode: DCO constant (K) for DCORSEL 0 to 4 Word DCO ER mode: DCO constant (K) for DCORSEL 5 System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 335: Adc Calibration Data
The temperature (Temp, °C) can be computed by Equation 4 for each of the reference voltages used in the ADC measurement: SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 336: Flash Information Descriptor
BSL Configuration Word Port interface configuration for UART Word Port interface configuration for SPI Word Port interface configuration for I System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 337: Arm Cortex-M4 Peripheral Id Register Description
As an example, the ROM table with IEEE 1149.1-complaint device IDCODE for the MSP432P401xx MCU is 0000-1011-1001-1010-1111-0000-0010-1111 (see Figure 5-9). Figure 5-9. Example of ROM PID Entries for MSP432P401xx MCU SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 338 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 339: Sys_Reboot_Ctl Register
Key to enable writes to bit 0. Bit 0 is written only if WKEY is 69h in the same write cycle. Reserved Reserved. Reads return 0h REBOOT Write 1 initiates a Reboot of the device SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 340: Sys_Nmi_Ctlstat Register
When the device enters LPM3.5/LPM4.5 modes of operation, this bit is always cleared to 0. In other words, the RSTn/NMI pin always assumes a reset functionality in LPM3.5/LPM4.5 modes. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 341: Sys_Wdtreset_Ctl Register
1b = WDT password violation event generates Hard reset TIMEOUT 0b = WDT timeout event generates Soft reset 1b = WDT timeout event generates Hard reset SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 342: Sys_Perihalt_Ctl Register
HALT_T16_0 0b = IP operation unaffected when CPU is halted 1b = freezes IP operation when CPU is halted System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 343: Sys_Sram_Size Register
Indicates the size of SRAM on the device. See the device-specific data sheet for the amount of SRAM available for the device. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 344: Sys_Sram_Numbanks Register
Indicates the number of SRAM banks on the device. See the device-specific data sheet for the number of SRAM banks available for the device. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 345: Sys_Sram_Numblocks Register
Indicates the number of SRAM blocks on the device. See the device-specific data sheet for the number of SRAM blocks available for the device. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 346: Sys_Mainflash_Size Register
Indicates the size of the Flash main memory on the device. See the device-specific data sheet for the size of flash main memory. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 347: Sys_Infoflash_Size Register
Indicates the size of the Flash main memory on the device. See the device-specific data sheet for the size of flash main memory. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 348: Sys_Dio_Gltflt_Ctl Register
GLTCH_EN 0b = Disables glitch filter on the digital I/Os 1b = Enables glitch filter on the digital I/Os System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 349: Sys_Secdata_Unlock
Write to unlock : 0x695A (only unlocks the same IP protected secure zone as that of the code writing to this register) Other writes : Lock SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 350: Sys_Sram_Banken_Ctl0 Register Description
Writes to this bit are allowed ONLY when the BNK_RDY bit in SYS_SRAM_STAT is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready, and writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 351 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 352: Sys_Sram_Banken_Ctl0 Register
When set to 1, bank enable bits for all banks below this bank are set to 1 as well. BNK0_EN When 1, enables Bank0 of the SRAM System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 353: Sys_Sram_Banken_Ctl1 Register
Writes to this bit are allowed ONLY when the BNK_RDY bit in SYS_SRAM_STAT is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready, and writes to this bit are ignored. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 354 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 355 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 356: Sys_Sram_Banken_Ctl2 Register
Writes to this bit are allowed ONLY when the BNK_RDY bit in SYS_SRAM_STAT is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready, and writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 357 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 358 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 359: Sys_Sram_Banken_Ctl3 Register
Writes to this bit are allowed ONLY when the BNK_RDY bit in SYS_SRAM_STAT is set to 1. If the bit is 0, it indicates that the SRAM banks are not ready, and writes to this bit are ignored. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 360 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 361 When set to 1, bank enable bits for all banks below this bank are set to 1 as well. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 362: Sys_Sram_Blkret_Ctl0 Register
Writes to this bit are allowed ONLY when the BLK_RDY bit of SYS_SRAM_STAT register is set to 1. If the SRAM_RDY bit is 0, writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 363 1b = Block1 of the SRAM is retained in LPM3 and LPM4 BLK0_RET Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 364: Sys_Sram_Blkret_Ctl1 Register
Writes to this bit are allowed ONLY when the BLK_RDY bit of SYS_SRAM_STAT register is set to 1. If the SRAM_RDY bit is 0, writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 365 0b = Block32 of the SRAM is not retained in LPM3 or LPM4 1b = Block32 of the SRAM is retained in LPM3 and LPM4 SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 366: Sys_Sram_Blkret_Ctl2 Register
Writes to this bit are allowed ONLY when the BLK_RDY bit of SYS_SRAM_STAT register is set to 1. If the SRAM_RDY bit is 0, writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 367 0b = Block64 of the SRAM is not retained in LPM3 or LPM4 1b = Block64 of the SRAM is retained in LPM3 and LPM4 SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 368: Sys_Sram_Blkret_Ctl3 Register
Writes to this bit are allowed ONLY when the BLK_RDY bit of SYS_SRAM_STAT register is set to 1. If the SRAM_RDY bit is 0, writes to this bit are ignored. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 369 0b = Block96 of the SRAM is not retained in LPM3 or LPM4 1b = Block96 of the SRAM is retained in LPM3 and LPM4 SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 370: Sys_Sram_Stat Register
This bit is automatically set to 0 whenever any of the SYS_SRAM_BANKEN_CTLx register bits are changed. It is set to 1 again after the SRAM controller has recognized the new BNKx_EN values System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 371: Sys_Master_Unlock Register
1000h are enabled or locked Read back : 0xA596 when unlocked, 0x0 when locked Write to unlock : 0x695A Other writes : Lock SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 372: Sys_Bootover_Req0 Register
Table 5-34. SYS_BOOTOVER_REQ0 Register Description Field Type Reset Description 31-0 REGVAL Value set by debugger, read and clear by the CPU System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 373: Sys_Bootover_Req1 Register
Reset Description 31-0 REGVAL Value is set by the debugger, and it is read and cleared by the CPU. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 374: Sys_Bootover_Ack Register
Table 5-36. SYS_BOOTOVER_ACK Register Description Field Type Reset Description 31-0 REGVAL Value set by CPU, read/clear by the debugger System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 375: Sys_Reset_Req Register
When written with 1, generates a Reboot Reset pulse to the device Reset Controller undefine When written with 1, generates a POR pulse to the device Reset Controller SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 376: Sys_Reset_Statover Register
The status of resets are still reflected in the system registers even when the reset overrides have been programmed. System Controller A (SYSCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 377: Sys_System_Stat Register
Indicates if JTAG and SWD Lock is active DBG_SEC_ACT undefine Indicates if the Debug Security is currently active Reserved undefine Reserved. SLAU356I – March 2015 – Revised June 2019 System Controller A (SYSCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 378 This chapter describes the operation of the clock system..........................Topic Page ................Clock System Introduction ..................Clock System Operation ....................CS Registers Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 379 Some of these are not only available as resources to the various system clocks but may also be used directly by various peripheral modules. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 380: Clock System Block Diagram
REFOCLK unconditional request REFO MODOSC REFOCLK MODCLK unconditional request MODCLK SYSCLK unconditional request SYSOSC REFO SYSCLK Figure 6-1. Clock System Block Diagram Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 381 For any active mode or LPM0 mode – LFXT_EN = 1 – LFXT is a source for ACLK (SELAx = 0). SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 382: Hfxtfreq Settings
If the PSEL bit associated with HFXIN is cleared, both HFXIN and HFXOUT ports are configured as general-purpose I/Os, and HFXT is disabled. HFXT is enabled under any of the following conditions: Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 383 – VLOCLK is a direct source for any module available in LPM3 or LPM3.5. • For LPM4.5 mode – VLO is off. VLO_EN bit has no effect in this mode. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 384 (MCLK, SMCLK, or HSMCLK). This is done because REFO is used to check the stability of the HFXTCLK and to control generation of HFXTIFG. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 385 For active modes (AM_LDO_VCOREx and AM_DCDC_VCOREx) or LPM0 modes (LPM0_LDO_VCOREx and LPM0_DCDC_VCOREx) – DCO_EN = 1 – DCO is a source for MCLK (SELMx = 3). SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 386 = DCO tune value in decimal DCOTUNE • FCAL = DCO frequency calibration value for range x for internal or external resistor mode CSDCOxRCAL Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 387 A peripheral module requests its clock sources from the clock system if required for its proper operation, regardless of the current power mode of operation (see Figure 6-2). SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 388: Module Clock Request System
HSMCLK selected & module_n enabled HSMCLK_REQEN_module_n HSMCLK_module_n HSMCLK unconditional request module_y HSMCLK_module_y Figure 6-2. Module Clock Request System Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 389 CS to the SYSCTL module. The fault flags must be cleared by software. The source of the fault can be identified by checking the individual fault flags. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 390: Oscillator Fault Logic
SET_LFXTIFG LFXTIFG To shared NMI/interrupt LFXTIE Reset CLR_LFXTIFG HFXT_OscFault / SET_HFXTIFG HFXTIFG HFXTIE Reset CLR_HFXTIFG Figure 6-3. Oscillator Fault Logic Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 391 The clock remains high until the next rising edge of the new clock. • The new clock source is selected and continues with a full high period. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 392: Switch Mclk From Dcoclk To Lfxtclk
This is indicated in the PCM module through the PMR_BUSY bit in the PCMCTL1 register. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 393: Cs Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 394: Cskey Register
Writing CSKEY with any other value causes CS registers to be locked and any writes to these registers are ignored, while reads are still performed. Always reads back A596h. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 395: Csctl0 Register
DCO frequency tuning select. 2s complement representation. Value represents an offset from the calibrated center frequency for the range selected by the DCORSEL bits. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 396: Csctl1 Register
011b = f(HSMCLK)/8 100b = f(HSMCLK)/16 101b = f(HSMCLK)/32 110b = f(HSMCLK)/64 111b = f(HSMCLK)/128 Reserved Reserved. Always reads as 0. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 397 101b = HFXTCLK 110b-111b = Reserved for future use. Defaults to DCOCLK. Not recommended for use to ensure future compatibilities. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 398: Csctl2 Register
Reserved. Always reads as 0. LFXTBYPASS LFXT bypass select. 0b = LFXT sourced by external crystal. 1b = LFXT sourced by external square wave. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 399 1h = Increased drive strength LFXT oscillator. 2h = Increased drive strength LFXT oscillator. 3h = Maximum drive strength and maximum current consumption LFXT oscillator. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 400: Csctl3 Register
Start flag counter for LFXT. Selects number of LFXT cycles before LFXTIFG can be cleared. 00b = 4096 cycles 01b = 8192 cycles 10b = 16384 cycles 11b = 32768 cycles Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 401: Csclken Register
ACLK system clock conditional request enable 0b = ACLK disabled regardless of conditional clock requests 1b = ACLK enabled based on any conditional clock requests. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 402: Csstat Register
VLOCLK system clock status 0b = Inactive 1b = Active MODCLK_ON MODCLK system clock status 0b = Inactive 1b = Active Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 403 1b = Active DCOBIAS_ON DCO bias status 0b = Inactive 1b = Active DCO_ON DCO status 0b = Inactive 1b = Active SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 404: Csie Register
0b = Interrupt disabled 1b = Interrupt enabled LFXTIE LFXT oscillator fault flag interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 405: Csifg Register
0b = No fault condition occurred after the last reset. 1b = LFXT fault. A LFXT fault occurred after the last reset. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 406: Csclrifg Register
1b = Clear pending interrupt flag CLR_LFXTIFG Clear LFXT oscillator fault interrupt flag. 0b = No effect 1b = Clear pending interrupt flag Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 407: Cssetifg Register
1b = Set pending interrupt flag SET_LFXTIFG Set LFXT oscillator fault interrupt flag. 0b = No effect 1b = Set pending interrupt flag SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 408: Csdcoercal0 Register
DCO frequency calibration for DCO frequency range (DCORSEL) 0 to 4. 15-2 Reserved Reserved. Always reads as 0. DCO_TCCAL DCO Temperature compensation calibration. Clock System (CS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 409: Csdcoercal1 Register
Reset Description 31-10 Reserved Reserved. Always reads as 0. DCO_FCAL_RSEL5 100h DCO frequency calibration for DCO frequency range (DCORSEL) 5. SLAU356I – March 2015 – Revised June 2019 Clock System (CS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 410 This chapter describes the operation of the Power Supply System (PSS)..........................Topic Page ............Power Supply System (PSS) Introduction ....................PSS Operation ....................PSS Registers Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 411: Pss Block Diagram
PSS. Regulator CORE VCCDET SVSMH Reference to POR reset logic to POR reset logic Figure 7-1. PSS Block Diagram SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 412 The behavior of the SVSMH according to these thresholds is best represented graphically. Figure 7-2 shows how the supervisor responds to supply failure conditions. Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 413: Supply Voltage Failure And Resulting Pss Action
See the device-specific data sheet for VCCDET threshold voltages. VCCDET is always active including the device operation in low power modes. SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 414 PSS. This interrupt can be handled as maskable or nonmaskable interrupt by configuring the respective SYSCTL and NVIC registers. Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 415: Pss Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 416: Psskey Register
Any other write value locks the PSS registers. Note: Registers can be read even when locked. Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 417: Pssctl0 Register
1b = Low power normal performance mode in LPM3, LPM4, and LPMx.5, full performance in all other modes. See the device-specific data sheet for response times. SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 418 RSTn pin reset within 200ns, the reset source may get elevated to a Reset High side due to insufficient power down time allowed for SVSMH. Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 419: Pssie Register
NMI may be seen due to an earlier dip in DVCC while interrupt was disabled. Reserved Reserved. Always read 0. SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 420: Pssifg Register
For more details, refer to the system control section in the appropriate device datasheet. Reserved Reserved. Always read 0. Power Supply System (PSS) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 421: Pssclrifg Register
SVSMH clear interrupt flag 0b = No effect 1b = Clear pending interrupt flag Reserved Reserved. Always read 0. SLAU356I – March 2015 – Revised June 2019 Power Supply System (PSS) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 422 Low-Power Reset ................8.24 Power Requests During Debug ............8.25 Wake-up Sources From Low-Power Modes ....................8.26 PCM Registers Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 423: Power Control Manager Interaction
It may not be possible to fulfill all requests and the PCM may deny some requests. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 424 Direct transitions between some of the power modes are not possible; see Section 8.5 for details on supported transitions. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 425 LPM0 entry. See Figure 8-4 for all valid LPM0 transitions. LPM0 modes are called as Sleep modes in Arm terminology. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 426 LPM3.5 and LPM4.5 transitions. LPM3.5 and LPM4.5 modes are called Stop or Shut Down modes in Arm terminology. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 427: Power Modes Summary For Msp432P401R And Msp432P401M Devices
Flash erase and program operations and SRAM bank enable or retention enable configuration changes must not be performed by application. DC/DC regulator cannot be used. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 428 (Stop or Shut Down) All low- and high-frequency clock sources are powered down. Device I/O pin states are latched and retained. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 429: Power Modes Summary For All Msp432P4Xx Devices Except Msp432P401R And Msp432P401M
Flash erase and program operations and SRAM bank enable or retention enable configuration changes must not be performed by application. DC/DC regulator cannot be used. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 430 Figure 8-2 and the detailed description of all supported power mode transitions is covered in the subsequent sections. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 431: High-Level Power-Mode Transitions
Figure 8-3 shows all active mode transitions that are supported. See the device-specific data sheet for active mode transition latencies. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 432: Valid Active Mode Transitions
LPM0 mode transitions supported. See the device-specific data sheet for LPM0 mode transition latencies. Figure 8-4. Valid LPM0 Transitions Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 433: Valid Lpm3 And Lpm4 Transitions
LPM3.5 and LPM4.5 mode transitions supported. See the device-specific data sheet for LPM3.5 and LPM4.5 mode transition latencies. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 434: Valid Lpm3.5 And Lpm4.5 Transitions
PCM for entry into LPM0, LPM3, and LPM4 modes of operation. The instructions are described briefly in the following sections. See the Arm documentation for complete details. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 435 The PCM Control 0 (PCMCTL0) register is the primary mechanism for changing power modes. The PCMCTL0 contains two fields: SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 436: Power Mode Selection
WFI, WFE, Sleep-on-exit Core voltage level 0 LPM4.5 mode LPM4.5 WFI, WFE, Sleep-on-exit Core voltage turned off X = don't care Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 437: Am Invalid Transition Nmi/Interrupt Enable
Table 8-6. PCM Static Clock Request Checks PCM Static Clock Request Checks Performed Device for... ACLK MCLK MSP432P401R and MSP432P401M SMCLK HSMCLK SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 438: Lpm Clock Checks Nmi/Interrupt Enable
5. When the PCM completes its operations, PMR_BUSY = 0 and the PCMCTL0 and CS registers are unlocked. Figure 8-7 shows the basic flow as described above. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 439: Active Mode Transition Flow
DCDC_ERROR_IE = 1 enables an NMI/interrupt to be executed when DCDC_ERROR_IFG = 1 (see Table 8-8). Table 8-8. DC/DC Error NMI/interrupt Enable DCDC_ERROR_IE DCDC_ERROR_IFG Response 0 or 1 None None NMI/interrupt SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 440 4. If this is a valid transition, PCM locks the PCMCTL0 and CS registers. In addition, it disables any new Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 441 LPM3 or LPM4 modes through regular interrupts. For example, UART receive complete interrupt or timer capture interrupt. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 442 The application should therefore treat these similar to other peripherals when entering LPM3.5 or LPM4.5 mode. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 443: Svsmh Performance And Power Modes
Static Optional Full performance Full performance mode is forced automatically by the PCM. SVSMHLP bit is do not care. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 444 The settings in the PCMCTL0 register reflect what the application code sees in normal operation. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 445: Wake-Up Sources From Low-Power Modes For Msp432P401R And Msp432P401M Devices
– – – – AES256 Any enabled interrupt – – – – Any enabled interrupt – – – – SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 446: Wake-Up Sources From Low-Power Modes For All Msp432P4Xx Devices Except Msp432P401R And Msp432P401M
WDT_A needs to be operated in interval timer mode during LPM3 and LPM3.5 modes for deterministic device operation. Refer to RTC_C chapter for specific wake-up sources from low power modes LPM3 and LPM3.5. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 447 LOCKLPM5 bit in case of LPM4.5 mode and both LOCKLPM5 and LOCKBKUP bits in case of LPM3.5 mode will be cleared upon wake-up due to the POR reset triggered by the wake-up event. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 448: 8.26 Pcm Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 449: Pcmctl0 Register
19h = LPM0_LF_VCORE1. Low-Frequency LPM0 at Core voltage setting 1. 1A-1Fh = Reserved. 20h = LPM3. 21h-3F = Reserved. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 450 Writing reserved values into LPMR will lead to non-deterministic device behavior Writing reserved values into AMR will lead to non-deterministic device behavior. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 451: Pcmctl1 Register
0b = Backup domain configuration defaults to reset condition. 1b = Backup domain configuration remains locked during LPM3.5 entry and exit. SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 452 0b = LPMx.5 configuration defaults to reset condition. 1b = LPMx.5 configuration remains locked during LPMx.5 entry and exit. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 453: Pcmie Register
Active Mode to LPM3 (LPMx.5 all transitions are allowed). 0b = Disabled 1b = Enabled SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 454: Pcmifg Register
LPM invalid transition flag. This flag is set if the requested Active Mode to LPM3 transition is invalid. Flag will remain set until cleared by software. Power Control Manager (PCM) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 455: Pcmclrifg Register
0b = No effect 1b = Clear flag CLR_LPM_INVALID_TR_IFG Clear LPM invalid transition flag. 0b = No effect 1b = Clear flag SLAU356I – March 2015 – Revised June 2019 Power Control Manager (PCM) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 456 Page ..................... Introduction ..........Common Operations Using the Flash Controller ..........Advanced Operations using the Flash Controller ....................FLCTL Registers Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 457 – The DMA has conditional access read permissions to the flash. If the device is not secure, or JTAG and SWD lock-based security is active, the DMA has full permissions to the entire flash space. If IP SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 458: Msp432 Driver Library Api For Flash Wait-State Configuration
(expected to be contiguous in nature) within the same 128-bit address boundary are serviced by the buffer. Hence, the flash accesses see wait-states only Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 459: Msp432 Driver Library Api For Flash Read Buffering Configuration
Table 9-4. MSP432 Driver Library API for Flash Sector Erase Operation MSP432 Driver Library API Function FlashCtl_eraseSector Erases a sector of MAIN or INFO flash memory. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 460: Msp432 Driver Library Api For Flash Mass Erase Operation
The MSP432P flash controller can be programmed to output data from the flash memory in different read modes. The different read modes supported on the device are: Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 461: Msp432 Driver Library Api For Setting Up Flash Read Modes
The pre-program-verify stage is not mandatory if the application knows that the flash location to be programed is already in erased state. However, post-program-verify is required following every program operation. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 462: Configuring The Auto-Verify Mode Through Direct Register Access
Sets up pre- or post-verification of burst and regular flash programming instructions FlashCtl_clearProgramVerification Clears pre- or post-verification of burst and regular flash programming instructions. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 463: Msp432 Driver Library Api For Enabling Program Operations
Disables word programming of flash memory. FlashCtl_isWordProgrammingEnabled Returns if word programming mode is enabled (and if it is, the specific mode) SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 464: Immediate And Full Word Program Flow
AVPRE = 1 or AVPST = 1? End of word programming Figure 9-1. Immediate and Full Word Program Flow Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 465: Pre-Verify Error Handling For Immediate And Full Word Program Flow
AVPST = 1? End of word programming Figure 9-2. Pre-Verify Error Handling for Immediate and Full Word Program Flow SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 466: Post-Verify Error Handling For Immediate And Full Word Program Flow
1 or AVPST = End of word programming Figure 9-3. Post-Verify Error Handling for Immediate and Full Word Program Flow Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 467 9.3.2.3.1 Software Flow for Burst Programming Mode Figure 9-4, Figure 9-5, and Figure 9-6 show the software flow to be followed for reliable burst programming mode. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 468: Burst Program Flow
Increment programing pulses used. num_prg_pls++; PRE_ERR = 1 or PST_ERR = 1 in FLCTL_PRGBRST_CTLSTAT? End of burst programming Figure 9-4. Burst Program Flow Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 469: Handling Auto-Verify Error Before The Burst Operation
Increment programing pulses used. num_prg_pls++; PST_ERR = 1? End of word programming Figure 9-5. Handling Auto-Verify Error Before the Burst Operation SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 470: Handling Auto-Verify Error After The Burst Operation
= 1 or PST_ERR = 1 in FLCTL_PRGBRST_CTLSTAT? End of burst programming Figure 9-6. Handling Auto-Verify Error After the Burst Operation Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 471: Msp432 Driver Library Api For Flash Erase Operations
An efficient software implementation of erase verification should use the burst read and compare feature of the FLCTL. See the example on erase verify in Section 9.3.3.2. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 472 Completion of immediate/full-word program operation (PRG) • Loss of data due to erroneous writes in Full Word Program mode (explained in Section 9.3.2.2) Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 473 This section concentrates on the effect of system/device level resets on the flash functionality. 9.3.7.1 Soft Reset (Class 3) A Soft Reset has no impact on the flash controller functionality. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 474 All current and outstanding program or erase operations are terminated. • All application settings in the flash Control registers are reset. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 475: Flctl Registers
Clear Interrupt Flag Register Section 9.4.40 0FCh FLCTL_SETIFG Set Interrupt Flag Register Section 9.4.41 100h FLCTL_READ_TIMCTL Read Timing Control Register Section 9.4.42 SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 476 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 477: Flctl_Power_Stat Register
101b = Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. 110b = Flash IP in Standby mode 111b = Flash IP in Current mirror boost state SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 478: Flctl_Bank0_Rdctl Register
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 479: Flctl_Bank0_Rdctl Register Description
0100b = Erase Verify All others = Reserved These bits are forced to 0h when the device is in 2T mode of operation. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 480: Flctl_Bank1_Rdctl Register
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 481: Flctl_Bank1_Rdctl Register Description
0100b = Erase Verify All others = Reserved These bits are forced to 0h when the device is in 2T mode of operation. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 482: Flctl_Rdbrst_Ctlstat Register
Writes to the START bit are ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 483: Flctl_Rdbrst_Startaddr Register
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 484: Flctl_Rdbrst_Len Register Description
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 485: Flctl_Rdbrst_Failaddr Register
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 486: Flctl_Rdbrst_Failcnt Register
This bit field is writable only when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 487: Flctl_Prg_Ctlstat Register
This bit is forced to 0h when the device is in low-frequency active and low-frequency LPM0 modes of operation SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 488: Flctl_Prgbrst_Ctlstat Register
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 489: Flctl_Prgbrst_Startaddr Register
Writes to the START bit are ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 490: Flctl_Prgbrst_Startaddr Register
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 491: Flctl_Prgbrst_Data0_0 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 492: Flctl_Prgbrst_Data0_2 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 493: Flctl_Prgbrst_Data1_0 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 494: Flctl_Prgbrst_Data1_2 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 495: Flctl_Prgbrst_Data2_0 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 496: Flctl_Prgbrst_Data2_2 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 497: Flctl_Prgbrst_Data3_0 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 498: Flctl_Prgbrst_Data3_2 Register Description
This bit field is writable only when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 499: Flctl_Erase_Ctlstat Register
Writes to the START bit are ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 500: Flctl_Erase_Sectaddr Register
This bit field is writable only when status (17:16) of the FLCTL_ERASE_CTLSTAT shows the Idle state. In all other cases, the bits remain locked so as to not disrupt an operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 501: Flctl_Bank0_Info_Weprot Register
FLCTL_ERASE_CTLSTAT all show the Idle state. In all other cases, the bits remain locked so as to not disrupt an erase or program operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 502: Flctl_Bank0_Main_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 503 NOTE: In case Bank0 of the Main Memory contains less than 32 sectors, upper bits behave as reserved. Refer to the appropriate data sheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 504: Flctl_Bank1_Info_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 505: Flctl_Bank1_Main_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits remain locked so as to not disrupt an erase or program operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 506 NOTE: In case Bank1 of the Main Memory contains less than 32 sectors, upper bits behave as reserved. Refer to the appropriate data sheet for the amount of Main Memory available on the device Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 507: Flctl_Bmrk_Ctlstat Register
Flash I_BMRK When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 508: Flctl_Bmrk_Ifetch Register
Type Reset Description 31-0 COUNT Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch) Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 509: Flctl_Bmrk_Dread Register
Reset Description 31-0 COUNT Reflects the number of Data Read operations to the Flash (increments by one on each read) SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 510: Flctl_Bmrk_Cmp Register Description
Reset Description 31-0 COUNT 0001_00 Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 511: Flctl_Ifg Register Description
If set to 1, indicates that the pre-program verify operation has detected an error RDBRST If set to 1, indicates that the Read Burst/Compare operation is complete SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 512: Flctl_Ie Register Description
RDBRST If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 513: Flctl_Clrifg Register Description
Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 514: Flctl_Setifg Register Description
Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG RDBRST Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 515: Flctl_Read_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 516: Flctl_Readmargin_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 517: Flctl_Prgver_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 518: Flctl_Ersver_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 519: Flctl_Program_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 520: Flctl_Erase_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5-MHz reference clock source Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 521: Flctl_Masserase_Timctl Register
Length of the time for which LDO Boost Signal is kept active All delays are in terms of clock cycles of a 5-MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller (FLCTL) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 522: Flctl_Burstprg_Timctl Register
Length of the Active phase for this operation Reserved Reserved for future use. All delays are in terms of clock cycles of a 5-MHz reference clock source Flash Controller (FLCTL) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 523 10.2 Common Operations Using the Flash Controller ..........10.3 Advanced Operations using the Flash Controller ................... 10.4 FLCTL_A Registers SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 524 – The CPU can issue data reads and writes to the entire flash memory region (unless the access is Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 525: Msp432 Driver Library Api For Flctl_A Wait-State Configuration
(expected to be contiguous in nature) within the same 128-bit address boundary are serviced by the buffer. Hence, the flash accesses see wait states only SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 526: Msp432 Driver Library Api For Flctl_A Read Buffering Configuration
Table 10-4. MSP432 Driver Library API for FLCTL_A Sector Erase Operation MSP432 Driver Library API Function FlashCtl_A_eraseSector Erases a sector of MAIN or INFO flash memory. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 527: Msp432 Driver Library Api For Flctl_A Mass Erase Operation
The MSP432P flash controller can be programmed to output data from the flash memory in different read modes. The different read modes supported on the device are: SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 528 The flash programming stage can be accomplished using any of the following advanced program modes: • Immediate write mode Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 529: Configuring The Auto-Verify Mode Through Direct Register Access
16 bytes of data ready for programming. The following steps explain how full-word programming mode should be used by the application: SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 530: Msp432 Driver Library Api For Enabling Flctl_A Program Operations
Disables word programming of flash memory. FlashCtl_A_isWordProgrammingEnabled Returns if word programming mode is enabled (and if it is, the specific mode) Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 531: Immediate And Full Word Program Flow
AVPRE = 1 or AVPST = 1? End of word programming Figure 10-1. Immediate and Full Word Program Flow SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 532: Pre-Verify Error Handling For Immediate And Full Word Program Flow
AVPST = 1? End of word programming Figure 10-2. Pre-Verify Error Handling for Immediate and Full Word Program Flow Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 533: Post-Verify Error Handling For Immediate And Full Word Program Flow
1 or AVPST = End of word programming Figure 10-3. Post-Verify Error Handling for Immediate and Full Word Program Flow SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 534 Figure 10-4, Figure 10-5, and Figure 10-6 show the software flow to be followed for reliable burst programming mode. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 535: Burst Program Flow
PRE_ERR = 1 or PST_ERR = 1 in FLCTL_PRGBRST_CTLSTAT? End of burst programming Figure 10-4. Burst Program Flow SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 536: Handling Auto-Verify Error Before The Burst Operation
Increment programing pulses used. num_prg_pls++; PST_ERR = 1? End of word programming Figure 10-5. Handling Auto-Verify Error Before the Burst Operation Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 537: Handling Auto-Verify Error After The Burst Operation
= 1 or PST_ERR = 1 in FLCTL_PRGBRST_CTLSTAT? End of burst programming Figure 10-6. Handling Auto-Verify Error After the Burst Operation SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 538: Msp432 Driver Library Api For Flctl_A Erase Operations
An efficient software implementation of erase verification should use the burst read and compare feature of the FLCTL. See the example of erase verify in Section 10.3.3.2. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 539 Pre-program auto-verify error (AVPRE) • Post-program auto-verify error (AVPST) • Completion of an immediate or full-word program operation (PRG) SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 540 This section describes the effects of device-level resets on the flash functionality. 10.3.7.1 Soft Reset (Class 3) A soft reset has no effect on the flash controller functionality. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 541 All current and outstanding program or erase operations are terminated. • All application settings in the flash control registers are reset. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 542 Section 10.4.46 118h FLCTL_ERASE_TIMCTL Erase Timing Control Register Section 10.4.47 11Ch FLCTL_MASSERASE_TIMCTL Mass Erase Timing Control Register Section 10.4.48 Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 543: Flctl_A Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 544: Flctl_Power_Stat Register
101b = Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. 110b = Flash IP in Standby mode 111b = Flash IP in Current mirror boost state Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 545: Flctl_Bank0_Rdctl Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 546 All others = Reserved. These bits will be forced to 0h when the device is in 2T mode of operation. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 547: Flctl_Bank1_Rdctl Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 548 All others = Reserved. These bits will be forced to 0h when the device is in 2T mode of operation. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 549: Flctl_Rdbrst_Ctlstat Register
Writes to the START bit will be ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 550: Flctl_Rdbrst_Startaddr Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 551: Flctl_Rdbrst_Len Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 552: Flctl_Rdbrst_Failaddr Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 553: Flctl_Rdbrst_Failcnt Register
This bit field is writable ONLY when burst status (17:16) of the FLCTL_RDBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 554: Flctl_Prg_Ctlstat Register
This bit will be forced to 0h when the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 555: Flctl_Prgbrst_Ctlstat Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 556 Writes to the START bit will be ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 557: Flctl_Prgbrst_Startaddr Register Description
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 558: Flctl_Prgbrst_Data0_0 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 559: Flctl_Prgbrst_Data0_2 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 560: Flctl_Prgbrst_Data1_0 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 561: Flctl_Prgbrst_Data1_2 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 562: Flctl_Prgbrst_Data2_0 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 563: Flctl_Prgbrst_Data2_2 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 564: Flctl_Prgbrst_Data3_0 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 565: Flctl_Prgbrst_Data3_2 Register
This bit field is writable ONLY when burst status (18:16) of the FLCTL_PRGBRST_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 566: Flctl_Erase_Ctlstat Register
Writes to the START bit will be ignored if the device is in Low-Frequency Active and Low-Frequency LPM0 modes of operation Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 567: Flctl_Erase_Sectaddr Register
This bit field is writable ONLY when status (17:16) of the FLCTL_ERASE_CTLSTAT shows the Idle state. In all other cases, the bits will remain locked so as to not disrupt an operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 568: Flctl_Bank0_Info_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 569: Flctl_Bank0_Main_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 570 NOTE: In case Bank0 of the Main Memory contains less than 32 sectors, upper bits will behave as reserved. Refer to the appropriate datasheet for amount of Main Memory available on the device Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 571: Flctl_Bank1_Info_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 572: Flctl_Bank1_Main_Weprot Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 573 NOTE: In case Bank1 of the Main Memory contains less than 32 sectors, upper bits will behave as reserved. Refer to the appropriate datasheet for the amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 574: Flctl_Bmrk_Ctlstat Register
Flash I_BMRK When 1, increments the Instruction Benchmark count register on each instruction fetch to the Flash Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 575: Flctl_Bmrk_Ifetch Register
Reset Description 31-0 COUNT Reflects the number of Instruction Fetches to the Flash (increments by one on each fetch) SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 576: Flctl_Bmrk_Dread Register
Description 31-0 COUNT Reflects the number of Data Read operations to the Flash (increments by one on each read) Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 577: Flctl_Bmrk_Cmp Register
Description 31-0 COUNT 0001_00 Reflects the threshold value that is compared against either the IFETCH or DREAD Benchmark Counters SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 578: Flctl_Ifg Register
If set to 1, indicates that the pre-program verify operation has detected an error RDBRST If set to 1, indicates that the Read Burst/Compare operation is complete Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 579: Flctl_Ie Register
If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 580: Flctl_Clrifg Register
Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG RDBRST Write 1 clears the corresponding interrupt flag bit in the FLCTL_IFG Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 581: Flctl_Setifg Register
Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG RDBRST Write 1 sets the corresponding interrupt flag bit in the FLCTL_IFG SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 582: Flctl_Read_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 583: Flctl_Readmargin_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 584: Flctl_Prgver_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 585: Flctl_Ersver_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 586: Flctl_Program_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 587: Flctl_Erase_Timctl Register
Length of the Setup phase for this operation All delays are in terms of clock cycles of a 5MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 588: Flctl_Masserase_Timctl Register
Length of the time for which LDO Boost Signal is kept active All delays are in terms of clock cycles of a 5MHz reference clock source Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 589: Flctl_Burstprg_Timctl Register
Reserved Reserved for future use. All delays are in terms of clock cycles of a 5MHz reference clock source SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 590: Flctl_Bank0_Main_Weprot0 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 591 NOTE: In case Bank0 of the Main Memory contains less than 32 sectors, upper bits will behave as reserved. Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 592: Flctl_Bank0_Main_Weprot1 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 593 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 594: Flctl_Bank0_Main_Weprot2 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 595 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 596: Flctl_Bank0_Main_Weprot3 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 597 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 598: Flctl_Bank0_Main_Weprot4 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 599 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 600: Flctl_Bank0_Main_Weprot5 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 601 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 602: Flctl_Bank0_Main_Weprot6 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 603 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 604: Flctl_Bank0_Main_Weprot7 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 605 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 606: Flctl_Bank1_Main_Weprot0 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 607 NOTE: In case Bank1 of the Main Memory contains less than 32 sectors, upper bits will behave as reserved. Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 608: Flctl_Bank1_Main_Weprot1 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 609 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 610: Flctl_Bank1_Main_Weprot2 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 611 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 612: Flctl_Bank1_Main_Weprot3 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 613 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 614: Flctl_Bank1_Main_Weprot4 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 615 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 616: Flctl_Bank1_Main_Weprot5 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 617 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 618: Flctl_Bank1_Main_Weprot6 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 619 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 620: Flctl_Bank1_Main_Weprot7 Register
FLCTL_ERASE_CTLSTAT ALL show the Idle state. In all other cases, the bits will remain locked so as to not disrupt an erase or program operation that is in progress. Flash Controller A (FLCTL_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 621 Refer to the appropriate datasheet for amount of Main Memory available on the device SLAU356I – March 2015 – Revised June 2019 Flash Controller A (FLCTL_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 622 This chapter describes the features and use of the MSP432P4xx DMA controller module..........................Topic Page ..................... 11.1 DMA Introduction ....................11.2 DMA Operation ....................11.3 DMA Registers SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 623 Triggers for each channel can be selected by the user. • Software trigger support for each channel • Raw and masked interrupts for optimal interrupt processing SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 624: Dma Block Diagram
11.2.2 AHB Master Interface The following sections describe the features of this interface • Transfer types • Transfer data width • Protection control • Address increments SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 625: Protection Signaling
32 bits. Table 11-2. Address Increments Packet Data Width (bits) Size of Address Increment byte, halfword, or word halfword or word word SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 626: Dma Signaling When Peripherals Use Pulse Requests
DMA request timing when a peripheral uses pulse signaling. Figure 11-2. DMA Signaling When Peripherals Use Pulse Requests Figure 11-2: • T1: The controller detects a request on channel C. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 627: Dma Signaling When Peripherals Use Level Requests
T7-T9: The controller performs the DMA transfer for channel C, where: – RD: Reads data – WD: Writes data • T9-T10: The controller writes the channel_cfg, where: SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 628: Ahb Bus Transfer Arbitration Interval
When the controller arbitrates, it determines the next channel to service by using the following information: • The channel number • The priority level, default or high, that is assigned to the channel SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 629: Polling Flowchart
Select channel that has the lowest channel the lowest channel number and is set to number high priority level Start DMA transfer Figure 11-4. Polling Flowchart SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 630: Dma Cycle Types
3. The controller sets dma_done[C] HIGH for one hclk cycle. If the channel is enabled for interrupts, then the DMA interrupts the host processor according to the interrupt configuration. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 632: Ping-Pong Example
6. The controller sets dma_done[C] HIGH for one hclk cycle and enters the arbitration process. If the channel is enabled for Interrupts, then the DMA interrupts the host processor according to the interrupt configuration. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 633 However, because the host processor has not configured the alternate data structure, and on completion of task D the controller set the cycle_ctrl bits to 000b, then the ping-pong DMA transaction completes. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 634: Channel_Cfg For A Primary Data Structure, In Memory Scatter-Gather Mode
Configures the state of HPROT when the controller writes the destination data [20:18] src_prot_ctrl Configures the state of HPROT when the controller reads the source data SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 635: Memory Scatter-Gather Example
100b. Because a data structure for a single channel consists of four words, 2 must be set to 4. In this example, there are four tasks, and therefore N is set to 16. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 636 DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the alternate data structure, without rearbitrating or dma_active[C] going LOW. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 637: Channel_Cfg For A Primary Data Structure, In Peripheral Scatter-Gather Mode
Because the R_power field is set to four, set N to be a multiple of four. The value given by N/4 is the number of times that the alternate data structure must be configured. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 638: Peripheral Scatter-Gather Example
2. The host processor writes the data structure for tasks A, B, C, and D to the memory locations that the primary src_data_end_ptr specifies. 3. The host processor enables the channel. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 639 2. It must compare the disabled channels list from step 1, with the record of the channels that have SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 640: Memory Map For 32 Channels, Including The Alternate Data Structure
The amount of system memory required depends on: • The number of DMA channels that the controller uses • If a DMA channel uses the alternate data structure SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 641: Address Bit Settings For The Channel Control Data Structure
Selects the control data configuration. The controller does not access this address location. If required, the host processor can use this memory location as system memory. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 642: Memory Map For Three Dma Channels, Including The Alternate Data Structure
0xXXXXX700, 0xXXXXX800, 0xXXXXX900, 0xXXXXXA00, 0xXXXXXB00, 0xXXXXXC00, 0xXXXXXD00, 0xXXXXXE00, 0xXXXXXF00 0xXXXXX000, 0xXXXXX200, 0xXXXXX400, 0xXXXXX600, 0xXXXXX800, 0xXXXXXA00, 0xXXXXXC00, 9-16 0xXXXXXE00 Where X is a hexadecimal. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 643: Channel_Cfg Bit Assignments
Figure 11-10. channel_cfg Bit Assignments Table 11-13 lists the bit assignments for this memory location. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 644: Channel_Cfg Bit Assignments
Set the bits to match the size of the source data: 00b = byte [25:24] src_size 01b = halfword 10b = word 11b = reserved SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 645 The controller updates this field immediately before entering the arbitration process. This enables the controller to store the number of outstanding DMA transfers that are necessary to complete the DMA cycle. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 646 = 00b and dst_inc = 00b • source address = src_data_end_ptr – n_minus_1 • destination address = dst_data_end_ptr – n_minus_1 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 647 In addition to the four interrupt lines, there is a dedicated interrupt line (DMA_ERR) from the DMA controller to the CPU that is triggered when the DMA receives a bus error response during any transfer. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 648: 11.3 Dma Registers
The reset value depends on the number of DMA channels available and if the integration test logic is included. The reset value depends on the number of DMA channels available. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 649: Dma_Device_Cfg Register
NUM_DMA_CHANNE Undefine Reflects the number of DMA channels available on the device Refer to appropriate device datasheet for the value in this field SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 650: Dma_Sw_Chtrig Register
Write 1 triggers DMA_CHANNEL11. Bit is auto-cleared when channel goes active. CH10 Write 1 triggers DMA_CHANNEL10. Bit is auto-cleared when channel goes active. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 651 The intent of providing a software trigger feature is to either allow software to completely control the DMA channel, or to emulate the DMA request/acknowledge functionality of the actual source that is mapped to that channel. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 652: Dma_Chn_Srccfg Register
Controls which device level DMA source is mapped to the channel input (bits higher than the number of available sources will be forced to r mode) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 653: Dma_Int1_Srccfg Register
INT0 If the number of channels is less than 32, all bits for channels that are not implemented should behave as reserved. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 654: Dma_Int2_Srccfg Register
INT0 If the number of channels is less than 32, all bits for channels that are not implemented should behave as reserved. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 655: Dma_Int3_Srccfg Register
INT0 If the number of channels is less than 32, all bits for channels that are not implemented should behave as reserved. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 656: Dma_Int0_Srcflg Register
If 1, indicates that Channel 0 was the source of DMA_INT0 NOTE: If the number of channels is less than 32, all bits for channels that are not implemented should behave as reserved. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 657: Dma_Int0_Clrflg Register
Write 1 clears the corresponding flag bit in the DMA_INT0_SRCFLG register. Write 0 has no effect CH10 Write 1 clears the corresponding flag bit in the DMA_INT0_SRCFLG register. Write 0 has no effect SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 658 Write 0 has no effect NOTE: If the number of channels is less than 32, all bits for channels that are not implemented should behave as reserved. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 659: Dma_Stat Register
1101b = Reserved 1110b = Reserved 1111b = Reserved RESERVED Reserved MASTEN Enable status of the controller 0b = Controller disabled 1b = Controller enabled SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 660: Dma_Cfg Register
When bit [n] = 0 then the corresponding HPROT is LOW. RESERVED Reserved MASTEN Enable status of the controller 0b = Controller disabled 1b = Controller enabled SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 661: Dma_Ctlbase Register
Table 11-25. DMA_CTLBASE Register Field Descriptions Field Type Reset Description 31-5 ADDR Pointer to the base address of the primary data structure. RESERVED Reserved SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 662: Dma_Altbase Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR Table 11-26. DMA_ALTBASE Register Field Descriptions Field Type Reset Description 31-0 ADDR Base address of the alternate data structure SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 663: Dma_Waitstat Register
31-0 WAITREQ Channel wait on request status. Read as: Bit [C] = 0 dma_waitonreq[C] is LOW. Bit [C] = 1 dma_waitonreq[C] is HIGH. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 664: Dma_Swreq Register
Bit [C] = 1 Creates a DMA request for channel C. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 665: Dma_Useburstset Register
Bit [C] = 1 Disables dma_sreq[C] from generating DMA requests. The controller performs 2 transfers. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 666: Dma_Useburstclr Register
Bit [C] = 1 Enables dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 667: Dma_Reqmaskset Register
Bit [C] = 1 Disables dma_req[C] and dma_sreq[C] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 668: Dma_Reqmaskclr Register
Bit [C] = 1 Enables dma_req[C] or dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 669: Dma_Enaset Register
Use the DMA_ENACLR Register to disable a channel. Bit [C] = 1 Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 670: Dma_Enaclr Register
DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 671: Dma_Altset Register
DMA cycle all the transfers that the alternate data structure specifies for the following DMA cycle types: ping-pong, memory scatter-gather, or peripheral scatter-gather. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 672: Dma_Altclr Register
DMA cycle all the transfers that the alternate data structure specifies for the following DMA cycle types: ping-pong, memory scatter-gather, or peripheral scatter-gather. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 673: Dma_Prioset Register
Bit [C] = 1 Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 674: Dma_Prioclr Register
Bit [C] = 1 Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 675: Dma_Errclr Register
Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted. SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 676 Topic Page ..................12.1 Digital I/O Introduction ..................12.2 Digital I/O Operation ....................12.3 I/O Configuration ..................12.4 Digital I/O Registers Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 677 When reading from ports that contain fewer than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 678 PxDIR, PxREN, and PxOUT for proper I/O configuration. Table 12-1. I/O Configuration PxDIR PxREN PxOUT I/O Configuration Input Input with pulldown resistor Input with pullup resistor Output Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 679: I/O Function Selection
PxIE bit is set. Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt. • Bit = 0: No interrupt is pending SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 680 The PxIES register configuration is a don't care and wake-up is triggered upon rising or falling edge of the wake-up event. Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 681 Optionally, configure input interrupt pins for wake-up from low-power modes. To wake the device from low-power modes, a general-purpose I/O port must contain an input port with interrupt and wake-up SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 682 NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG flags are set, and it cannot be determined which port caused the I/O wake-up. Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 683: 12.4 Digital I/O Registers
Section 12.4.10 or PAIES_L P1IE Port 1 Interrupt Enable Section 12.4.11 or PAIE_L P1IFG Port 1 Interrupt Flag Section 12.4.12 or PAIFG_L SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 684 Section 12.4.10 or PBIES_L P3IE Port 3 Interrupt Enable Section 12.4.11 or PBIE_L P3IFG Port 3 Interrupt Flag Section 12.4.12 or PBIFG_L Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 685 Section 12.4.10 or PCIES_L P5IE Port 5 Interrupt Enable Section 12.4.11 or PCIE_L P5IFG Port 5 Interrupt Flag Section 12.4.12 or PCIFG_L SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 686 Section 12.4.10 or PDIES_L P7IE Port 7 Interrupt Enable Section 12.4.11 or PDIE_L P7IFG Port 7 Interrupt Flag Section 12.4.12 or PDIFG_L Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 687 Section 12.4.10 or PEIES_L P9IE Port 9 Interrupt Enable Section 12.4.11 or PEIE_L P9IFG Port 9 Interrupt Flag Section 12.4.12 or PEIFG_L SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 688 Section 12.4.10 or PEIES_H P10IE Port 10 Interrupt Enable Section 12.4.11 or PEIE_H P10IFG Port 10 Interrupt Flag Section 12.4.12 or PEIFG_H Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 689 Port A Interrupt Edge Select PAIES_L PAIES_H PAIE Port A Interrupt Enable PAIE_L PAIE_H PAIFG Port A Interrupt Flag PAIFG_L PAIFG_H SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 690 Port B Interrupt Edge Select PBIES_L PBIES_H PBIE Port B Interrupt Enable PBIE_L PBIE_H PBIFG Port B Interrupt Flag PBIFG_L PBIFG_H Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 691 Port C Interrupt Edge Select PCIES_L PCIES_H PCIE Port C Interrupt Enable PCIE_L PCIE_H PCIFG Port C Interrupt Flag PCIFG_L PCIFG_H SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 692 Port D Interrupt Edge Select PDIES_L PDIES_H PDIE Port D Interrupt Enable PDIE_L PDIE_H PDIFG Port D Interrupt Flag PDIFG_L PDIFG_H Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 693 Port E Interrupt Edge Select PEIES_L PEIES_H PEIE Port E Interrupt Enable PEIE_L PEIE_H PEIFG Port E Interrupt Flag PEIFG_L PEIFG_H SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 694 32-bit read or write access to this module causes a bus error. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 695: Pxiv Register
0Eh = Interrupt Source: Port x.6 interrupt; Interrupt Flag: PxIFG.6 10b = Interrupt Source: Port x.7 interrupt; Interrupt Flag: PxIFG.7; Interrupt Priority: Lowest SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 696: Pxin Register
Table 12-7. PxDIR Register Description Field Type Reset Description PxDIR Port X direction. 0b = Port configured as input 1b = Port configured as output Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 697: Pxren Register
For example, if P1SEL1.5 = 1 and P1SEL0.5 = 0, then the secondary module function is selected for P1.5. See PxSEL1 for the definition of each value. SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 698: Pxsel1 Register
Port X interrupt edge select 0b = PxIFG flag is set with a low-to-high transition. 1b = PxIFG flag is set with a high-to-low transition. Digital I/O SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 699: Pxie Register
Table 12-15. PxIFG Register Description Field Type Reset Description PxIFG Port X interrupt flag 0b = No interrupt is pending. 1b = Interrupt is pending. SLAU356I – March 2015 – Revised June 2019 Digital I/O Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 700 ........................... Topic Page ..............13.1 Port Mapping Controller Introduction ..............13.2 Port Mapping Controller Operation ....................13.3 PMAP Registers Port Mapping Controller (PMAP) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 701 I/O function by changing PxSEL0.y and PxSEL1.y bits to 0. SLAU356I – March 2015 – Revised June 2019 Port Mapping Controller (PMAP) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 702: Examples For Port Mapping Mnemonics And Functions
I2C data (open drain and direction controlled by eUSCI) PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI) PM_UCB0STE eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI) Port Mapping Controller (PMAP) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 703 With PxSEL.y = 1 and PxDIR.y = 1 PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals SLAU356I – March 2015 – Revised June 2019 Port Mapping Controller (PMAP) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 704: 13.3 Pmap Registers
Port mapping register, P7.0 and P7.1 Read/write Half-word Section 13.3.10 P7MAP23 Port mapping register, P7.2 and P7.3 Read/write Half-word Section 13.3.10 Port Mapping Controller (PMAP) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 705 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Port Mapping Controller (PMAP) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 706: Pmapkeyid Register
PMAPx Selects secondary port function for P1.x. Settings and reset value are device- dependent; see the device-specific data sheet. Port Mapping Controller (PMAP) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 707: P2Map0 To P2Map7 Register
Figure 13-7. P5MAP0 to P5MAP7 Register PMAPx If not all bits are required to decode all provided functions, the unused bits are r-0. SLAU356I – March 2015 – Revised June 2019 Port Mapping Controller (PMAP) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 708: P6Map0 To P6Map7 Register
Description 15-0 PMAPx undef Selects secondary port function. Settings and reset value are device-dependent; see the device-specific data sheet. Port Mapping Controller (PMAP) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 709 ........................... Topic Page ............... 14.1 Capacitive Touch IO Introduction ................14.2 Capacitive Touch IO Operation ..................14.3 CapTouch Registers SLAU356I – March 2015 – Revised June 2019 Capacitive Touch IO (CAPTIO) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 710: Capacitive Touch Io Principle
DVCC Direction Control PxOUT.y Output Signal Px.y Cap. Input Signal Capacitive Touch Signal Figure 14-1. Capacitive Touch IO Principle Capacitive Touch IO (CAPTIO) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 711: Capacitive Touch Io Block Diagram
It is possible to scan to successive port pins by incrementing the low byte of the Capacitive Touch IO control register CAPTIOCTL_L by 2. SLAU356I – March 2015 – Revised June 2019 Capacitive Touch IO (CAPTIO) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 712: 14.3 Captouch Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Capacitive Touch IO (CAPTIO) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 713: Captioxctl Register
011b = Px.3 100b = Px.4 101b = Px.5 110b = Px.6 111b = Px.7 Reserved Reserved. Always reads 0. SLAU356I – March 2015 – Revised June 2019 Capacitive Touch IO (CAPTIO) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 714 This chapter describes the operation and use of the CRC32 module..........................Topic Page ........15.1 Cyclic Redundancy Check (CRC32) Module Introduction ................15.2 CRC Checksum Generation ....................15.3 CRC32 Registers CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 715: Lfsr Implementation Of Crc-Ccitt As Defined In Standard (Bit0 Is Msb)
The checksum is stored in the MCU memory and is used to check the correctness of the CRC operation result. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 716 CRC engine. If the checksum itself (with reversed bit order) is included in the CRC operation (as data written to CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 717: 15.3 Crc32 Registers
32-bit read or write access to this module causes a bus error. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 718: Crc32Di Register
Data input for CRC32 Computation. Data written to the register is included to the present signature in the CRC32INIRES_HI and CRC32INIRES_LO registers according to the CRC32-ISO3309 standard. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 719: Crc32Dirb Register
CRC32 data in bit reversed. Data written to the register is included to the present signature in the CRC32INIRES_HI and CRC32INIRES_LO registers according to the CRC32-ISO3309 standard. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 720: Crc32Inires_Lo Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 721: Crc32Inires_Hi Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 722: Crc32Resr_Lo Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 723: Crc32Resr_Hi Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 724: Crc16Di Register
CRC16 data in. Data written to the CRC16DI register is included to the present signature in the CRC16INIRES register according to the CRC16-CCITT standard. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 725: Crc16Dirb Register
CRC16INIRES and CRC16RESR registers according to the CRC-CCITT standard. Reading the register returns the register CRC16DI content. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 726: Crc16Inires Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. CRC32 Module SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 727: Crc16Resr Register
This register is updated with the final signature value one cycle after the last data input value is written to the CRC32DI or CRC32DIRB registers. Application should wait for this one cycle delay before reading the result. SLAU356I – March 2015 – Revised June 2019 CRC32 Module Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 728 It supports key lengths of 128 bits, 192 bits, and 256 bits. This chapter describes the AES256 accelerator..........................Topic Page ................16.1 AES Accelerator Introduction ................16.2 AES Accelerator Operation ..................... 16.3 AES256 Registers AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 729: Aes Accelerator Block Diagram
AESAXDIN AESAKEY 128-bit 256-bit AES State AES Key Encryption and Decyption Memory Memory Core AESADOUT Figure 16-1. AES Accelerator Block Diagram SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 730: Aes State Array Input And Output
However, it is possible to write one of the registers using byte access and another using half-word access. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 731 If AESAXDIN is used to write the last byte or half-word of the state, encryption or decryption starts automatically. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 732 The AES module's encrypt or decrypt operations are triggered if the state was completely written to the AESADIN or AESAXDIN registers. Alternatively, the bit AESDINWR can be set to trigger a operation if AESCMEN = 0. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 733: Aes Encryption Process For 128-Bit Key
AESADIN register to a plaintext that can be read from the AESADOUT register using the cipher key provided in the AESAKEY register. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 734: Aes Decryption Process Using Aesopx = 01 For 128-Bit Key
AESOPx = 10, then the precalculated key can be used together with the decryption operation AESOPx = 11. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 735: Aes Decryption Process Using Aesopx = 10 And 11 For 128-Bit Key
The AES128, AES192, or AES256 algorithm operates not only on the state, but also on the key. To avoid the need of reloading the key for each encryption or decryption, a key buffer is included in the AES accelerator. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 736 128 bit are written decryption until 128 bit are read from until 128 bit are written to to AESAXIN AESADOUT AESAXDIN AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 737: Aes Trigger 0-2' Operation When Aescmen = 1
DMA channel. The DMA counter must be loaded with a multiple of 8 for half-word mode or a multiple of 16 for byte mode. The DMA priorities of DMA_A, DMA_B, and DMA_C do not play any role. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 738: Ecb Encryption
DMA1: Triggered by AES trigger 1, Source: plaintext, Destination: AESADIN, Size: num_blocks*8 half-words Start encryption: AESBLKCNT= num_blocks; End of encryption: DMA0IFG=1 AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 739: Ecb Decryption
DMA1: Triggered by AES trigger 1, Source: ciphertext, Destination: AESADIN, Size: num_blocks*8 half-words Start decryption: AESBLKCNT= num_blocks; End of decryption: DMA0IFG=1 SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 740: Cbc Encryption
DMA1: Triggered by AES trigger 1, Source: plaintext, Destination: AESAXDIN, Size: num_blocks*8 half-words Start encryption: AESBLKCNT= num_blocks; End of encryption: DMA0IFG=1 AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 741: Cbc Decryption
DMA0: // Write previous cipher text into AES module Triggered by AES trigger 0, Source: ciphertext, Destination: AESAXIN, Size: (num_blocks-1)*8 half-words End of decryption: DMA1IFG=1 SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 742: Ofb Encryption
Source: plaintext, Destination: AESAXDIN, Size: num_blocks*8 half-words Start encryption: AESBLKCNT= num_blocks; Trigger encryption by setting AESDINWR= 1; End of encryption: DMA1IFG=1 AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 743: Ofb Decryption
Source: ciphertext, Destination: AESAXDIN, Size: num_blocks*8 half-words Start decryption: AESBLKCNT= num_blocks; Trigger decryption by setting AESDINWR= 1; End of decryption: DMA1IFG=1 SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 744: Cfb Encryption
Source: AESADOUT, Destination: ciphertext, Size: num_blocks*8 half-words Start encryption: AESBLKCNT= num_blocks; Trigger encryption by setting AESDINWR= 1; End of encryption: DMA1IFG=1 AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 745: Cfb Decryption
Source: ciphertext, Destination: AESADIN, Size: num_blocks*8 half-words Start decryption: AESBLKCNT= num_blocks; Trigger decryption by setting AESDINWR= 1; End of decryption: DMA1IFG=1 SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 746: 16.3 Aes256 Registers
32-bit read or write access to this module causes a bus error. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 747: Aesactl0 Register
01b = AES192. The key size is 192 bit. 10b = AES256. The key size is 256 bit. 11b = Reserved SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 748 10b = Generate first round key required for decryption. 11b = Decryption. The provided key is the first round key required for decryption. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 749: Aesactl1 Register
The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 750: Aesastat Register
1 = All bytes written AESBUSY AES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 751: Aesakey Register
AESAKEY_L is written as byte. Do not mix half-word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 752: Aesadin Register
AES data in byte n when AESADIN is written as half-word. AES next data in byte when AESADIN_L is written as byte. Do not mix half-word and byte access. Always reads as zero. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 753: Aesadout Register
AES data out byte n when AESADOUT is read as half-word. AES next data out byte when AESADOUT_L is read as byte. Do not mix half-word and byte access. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 754: Aesaxdin Register
AES data in byte n when AESAXDIN is written as half-word. AES next data in byte when AESAXDIN_L is written as byte. Do not mix half-word and byte access. Always reads as zero. AES256 Accelerator SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 755: Aesaxin Register
AES data in byte n when AESAXIN is written as half-word. AES next data in byte when AESAXIN_L is written as byte. Do not mix half-word and byte access. Always reads as zero. SLAU356I – March 2015 – Revised June 2019 AES256 Accelerator Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 756: Wdt_A Registers
The watchdog timer is implemented in all devices..........................Topic Page ..................17.1 WDT_A Introduction ..................... 17.2 WDT_A Operation ..................... 17.3 WDT_A Registers Watchdog Timer (WDT_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 757 Password-protected access to the Watchdog Timer Control (WDTCTL) register • Selectable clock source • Can be stopped to conserve power Figure 17-1 shows the watchdog timer block diagram. SLAU356I – March 2015 – Revised June 2019 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 758: Watchdog Timer Block Diagram
WDTIS2 WDTIS1 WDTIS0 SMCLK request Clock ACLK request Request VLOCLK request Logic BCLK request Figure 17-1. Watchdog Timer Block Diagram Watchdog Timer (WDT_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 759 The watchdog timer should be halted before changing the clock source to avoid a possible incorrect interval. SLAU356I – March 2015 – Revised June 2019 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 760: Wdt_A Clock Sources
The WDT_A may be used either in watchdog or interval timer mode when the device is in one of the LPM0 modes of operation. All clock sources as listed in Table 17-1 are available. Watchdog Timer (WDT_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 761 17.2.6.5 WDT_A Operation in LPM4 and LPM4.5 Modes The WDT_A functionality is not available in LPM4 and LPM4.5 modes. SLAU356I – March 2015 – Revised June 2019 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 762 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Watchdog Timer (WDT_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 763: Wdtctl Register
CS does not stop the clock to the WDT_A module. In the Interval time mode, ACLK and SMCLK clock requests are always conditional from WDT_A module. SLAU356I – March 2015 – Revised June 2019 Watchdog Timer (WDT_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 764 This chapter describes the features and functionality of Timer32..........................Topic Page ..................... 18.1 Introduction ..................18.2 Functional Description ......................18.3 Operation ..................18.4 Interrupt Generation ..................... 18.5 Timer32 Registers Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 765 This enables the timer to be clocked at different frequencies. SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 766: Prescale Clock Enable Generation
TIMINTC, provides an additional interrupt condition from the Timer32 peripheral. Thus, the module supports three interrupts in total – TIMINT1, TIMINT2, and TIMINTC. Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 767: 18.5 Timer32 Registers
NOTE: This is a 32-bit module and can be accessed ONLY through word (32-bit) access. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 768: T32Load1 Register
LOAD rw-0 Table 18-2. T32LOAD1 Register Description Field Type Reset Description 31-0 LOAD The value from which the Timer 1 counter decrements Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 769: T32Value1 Register
VALUE r-FFFFFFFFh Table 18-3. T32VALUE1 Register Description Field Type Reset Description 31-0 VALUE FFFFFFFFh Reports the current value of the decrementing counter SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 770: T32Control1 Register
0b = 16-bit counter 1b = 32-bit counter ONESHOT Selects one-shot or wrapping counter mode 0b = wrapping mode 1b = one-shot mode Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 771: T32Intclr1 Register
Table 18-5. T32INTCLR1 Register Description Field Type Reset Description 31-0 INTCLR Any write to the T32INTCLR1 register clears the interrupt output from the counter. SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 772: T32Ris1 Register
Reserved Reserved RAW_I Table 18-6. T32RIS1 Register Description Field Type Reset Description 31-1 Reserved Reserved RAW_IFG Raw interrupt status from the counter Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 773: T32Mis1 Register
Figure 18-7. T32MIS1 Register Reserved Reserved Table 18-7. T32MIS1 Register Description Field Type Reset Description 31-1 Reserved Reserved Enabled interrupt status from the counter SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 774: T32Bgload1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BGLOAD rw-0 Table 18-8. T32BGLOAD1 Register Description Field Type Reset Description 31-0 BGLOAD Contains the value from which the counter decrements Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 775: T32Load2 Register
LOAD rw-0 Table 18-9. T32LOAD2 Register Description Field Type Reset Description 31-0 LOAD The value from which the Timer 2 counter decrements SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 776: T32Value2 Register
VALUE r-FFFFFFFFh Table 18-10. T32VALUE2 Register Description Field Type Reset Description 31-0 VALUE FFFFFFFFh Reports the current value of the decrementing counter Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 777: T32Control2 Register
0b = 16-bit counter 1b = 32-bit counter ONESHOT Selects one-shot or wrapping counter mode 0b = wrapping mode 1b = one-shot mode SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 778: T32Intclr2 Register
Table 18-12. T32INTCLR2 Register Description Field Type Reset Description 31-0 INTCLR Any write to the T32INTCLR2 register clears the interrupt output from the counter. Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 779: T32Ris2 Register
Reserved Reserved RAW_I Table 18-13. T32RIS2 Register Description Field Type Reset Description 31-1 Reserved Reserved RAW_IFG Raw interrupt status from the counter SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 780: T32Mis2 Register
Figure 18-14. T32MIS2 Register Reserved Reserved Table 18-14. T32MIS2 Register Description Field Type Reset Description 31-1 Reserved Reserved Enabled interrupt status from the counter Timer32 SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 781: T32Bgload2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BGLOAD rw-0 Table 18-15. T32BGLOAD2 Register Description Field Type Reset Description 31-0 BGLOAD Contains the value from which the counter decrements SLAU356I – March 2015 – Revised June 2019 Timer32 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 782 (see the device-specific data sheet). This chapter describes the operation and use of the Timer_A module..........................Topic Page ..................19.1 Timer_A Introduction .................... 19.2 Timer_A Operation .................... 19.3 Timer_A Registers Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 783 = 0. The suffix n, where n = 0 to 6, represents the specific capture/compare registers associated with the Timer_A instantiation. SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 784: Timer_A Block Diagram
D Set Q Unit4 OUT6 Signal EQU0 Timer Clock Reset OUTMOD Copyright © 2016, Texas Instruments Incorporated Figure 19-1. Timer_A Block Diagram Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 785 TAxCCR0. In this scenario, the timer starts incrementing in the up direction from zero. SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 786: Up Mode
However, one additional count may occur before the counter rolls to zero. Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 787: Continuous Mode
TAxCCR1b TAxCCR1c TAxCCR0d TAxCCR0b TAxCCR0c 0FFFFh TAxCCR1a TAxCCR1d TAxCCR0a Figure 19-6. Continuous Mode Time Intervals SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 788: Up/Down Mode
When the timer is counting in the up direction and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 789: Output Unit In Up/Down Mode
Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 19-10). SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 790: Capture Signal (Scs = 1)
Capture Read and No Capture Capture Clear Bit COV in Register TAxCCTLn Second Capture Idle Taken COV = 1 Figure 19-11. Capture Cycle Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 791: Output Modes
The output is reset when the timer counts to the TAxCCRn value. It is set when the timer Reset/Set counts to the TAxCCR0 value. SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 792: Output Example - Timer In Up Mode
Output Mode 7: Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events TAIFG TAIFG TAIFG Figure 19-12. Output Example – Timer in Up Mode Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 793: Output Example - Timer In Continuous Mode
Output Mode 6: Toggle/Set Output Mode 7: Reset/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events Figure 19-13. Output Example – Timer in Continuous Mode SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 794: Output Example - Timer In Up/Down Mode
NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 795 TAxIV register, TAxCCR1 CCIFG is reset automatically. After the completion of TAxCCR1 CCIFG interrupt service routine, the TAxCCR2 CCIFG flag generates another interrupt. SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 796: Timer_A Registers
NOTE: This is a 16-bit module and must be accessed ONLY through half-word (16 bit) access. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 797: Taxctl Register
Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0b = Interrupt disabled 1b = Interrupt enabled TAIFG Timer_A interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 798: Taxr Register
Table 19-5. TAxR Register Description Field Type Reset Description 15-0 TAxR Timer_A register. The TAxR register is the count of Timer_A. Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 799: Taxcctl0 To Taxcctl6 Register
Output. For output mode 0, this bit directly controls the state of the output. 0b = Output low 1b = Output high SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 800 0b = No capture overflow occurred 1b = Capture overflow occurred CCIFG Capture/compare interrupt flag 0b = No interrupt pending 1b = Interrupt pending Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 801: Taxccr0 To Taxccr6 Register
0Ch = Interrupt Source: Capture/compare 6; Interrupt Flag: TAxCCR6 CCIFG 0Eh = Interrupt Source: Timer overflow; Interrupt Flag: TAxCTL TAIFG; Interrupt Priority: Lowest SLAU356I – March 2015 – Revised June 2019 Timer_A Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 802: Taxex0 Register
011b = Divide by 4 100b = Divide by 5 101b = Divide by 6 110b = Divide by 7 111b = Divide by 8 Timer_A SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 803 Low-Power modes like LPM3 and LPM3.5. This chapter describes the RTC_C module..........................Topic Page ..................20.1 RTC_C Introduction ....................20.2 RTC_C Operation ....................20.3 RTC_C Registers SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 804 Most RTC_C module registers have no initial condition. These registers must be configured by user software before use. Figure 20-1 shows the RTC_C block diagram. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 805: Rtc_C Block Diagram
Calendar RTCYEARH RTCYEARL RTCMON RTCDAY Set_RTCAIFG Alarm RTCADOW RTCADAY RTCAHOUR RTCAMIN Figure 20-1. RTC_C Block Diagram SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 806 RTCADAY, RTCAHOUR and RTCAMIN, the alarm is enabled. Once enabled, the RTCAIFG is set when the time count transitions from 06:29:59 to 06:30:00 and the RTCDAY equals 5. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 807 The RTCRDYIFG flag is reset automatically when the interrupt is serviced or can be reset with software. SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 808 32-kHz oscillator is not available for CPU interrupt in low-power modes if an oscillator failure occurs. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 809 A hybrid software and hardware approach can be followed to achieve temperature compensation for RTC. SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 810 RTCTCMP again when RTCTCRDY is set. Figure 20-2. shows the scheme for real-time clock offset error calibration and temperature compensation. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 811: Rtc_C Offset Error Calibration And Temperature Compensation
RTCTCMP register. The value written into RTCTCMP in this case would be effective until it is updated again by software. SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 812 Also the fault detection for the oscillator remains functional within RTC. If during LPM3.5 a fault occurs and the RTCOFIE was set before entering LPM3.5, a wake-up event is issued. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 813 Read not retained Section 20.3.31 Real-Time Clock Seconds, RTCTIM0 Read/write retained Minutes RTCSEC Real-Time Clock Seconds Read/write retained Section 20.3.7 SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 814: Rtc_C Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 815: Rtcctl0_L Register
RTCRDYIFG Real-time clock ready interrupt flag 0b = RTC cannot be read safely 1b = RTC can be read safely SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 816: Rtcctl0_H Register
Real-time clock key. This register should be written with A5h to unlock RTC. Any write with value other than A5h locks the module. Reads from this register always return 96h. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 817: Rtcctl1 Register
00b = Minute changed 01b = Hour changed 10b = Every day at midnight (00:00) 11b = Every day at noon (12:00) SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 818: Rtcctl3 Register
00b = No frequency output to RTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 819: Rtcocal Register
(RTCOCALS = 1) or –1-ppm (RTCOCALS = 0) adjustment in frequency. Maximum effective calibration value is ±240 ppm. Values written above ±240 ppm are ignored by hardware. SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 820: Rtctcmp Register
±240 ppm are ignored by hardware. Changing the sign-bit by writing to RTCTCMP_H becomes effective only after also writing RTCTCMP_L. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 821: Rtcsec Register
Seconds – high digit (0 to 5) Seconds – low digit undefined Seconds – low digit (0 to 9) SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 822: Rtcmin Register
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 823: Rtchour Register
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 824: Rtcdow Register
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 825: Rtcmon Register
Month – high digit (0 or 1) Month – low digit undefined Month – low digit (0 to 9) SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 826: Rtcyear Register
Century – low digit (0 to 9) Decade undefined Decade (0 to 9) Year – lowest digit undefined Year – lowest digit (0 to 9) Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 827: Rtcamin Register
Minutes – high digit (0 to 5) Minutes – low digit undefined Minutes – low digit (0 to 9) SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 828: Rtcahour Register
Hours – high digit (0 to 2) Hours – low digit undefined Hours – low digit (0 to 9) Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 829: Rtcadow Register
Day of month – high digit (0 to 3) digit Day of month – low undefined Day of month – low digit (0 to 9) digit SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 830: Rtcps0Ctl Register
Prescale timer 0 interrupt flag. This interrupt can be used as an LPM3 or LPM3.5 wake-up event. 0b = No time event occurred 1b = Time event occurred Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 831: Rtcps1Ctl Register
Prescale timer 1 interrupt flag. This interrupt can be used as an LPM3 or LPM3.5 wake-up event. 0b = No time event occurred 1b = Time event occurred SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 832: Rtcps0 Register
Figure 20-32. RTCPS1 Register RT1PS Table 20-31. RTCPS1 Register Description Field Type Reset Description RT1PS undefined Prescale timer 1 counter value Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 833: Rtciv Register
0Ch = Interrupt Source: RTC prescaler 1; Interrupt Flag: RT1PSIFG 0Eh = Reserved 10h = Reserved ; Interrupt Priority: Lowest SLAU356I – March 2015 – Revised June 2019 Real-Time Clock (RTC_C) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 834: Rtcbin2Bcd Register
Description 15-0 BCD2BINx Read: 12-bit binary conversion of previously written 16-bit BCD number. Write: 16-bit BCD number to be converted. Real-Time Clock (RTC_C) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 835 LCD controller. This chapter describes the REF_A module..........................Topic Page ..................21.1 REF_A Introduction ..................21.2 Principle of Operation ....................21.3 REF_A Registers SLAU356I – March 2015 – Revised June 2019 Reference Module (REF_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 836: Ref_A Block Diagram
Request Reference 1.2 V, 1.45 V, 2.5 V Switch REFVSEL REFGENREQ REFBGOT REFGENOT REFON BGMODE Figure 21-1. REF_A Block Diagram Reference Module (REF_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 837 The generation of the buffered bandgap voltage can be triggered by a timer or by software to make sure the reference voltage is ready when an analog module requires it. SLAU356I – March 2015 – Revised June 2019 Reference Module (REF_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 838 ADC conversion and the large buffer remains disabled. The small buffer can operate in burst mode as well by setting ADC14REFBURST = 1. Reference Module (REF_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 839 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Reference Module (REF_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 840: Refctl0 Register
Temperature sensor disabled. Can be modified only when REFGENBUSY = 0. 0b = Temperature sensor enabled 1b = Temperature sensor disabled to save power Reference Module (REF_A) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 841 Reference enable. Can be modified only when REFGENBUSY = 0. 0b = Disables reference if no other reference requests are pending. 1b = Enables reference in static mode. SLAU356I – March 2015 – Revised June 2019 Reference Module (REF_A) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 842 This chapter describes the operation of the Precision ADC module..........................Topic Page ................22.1 Precision ADC Introduction ................... 22.2 Precision ADC Operation ....................22.3 ADC14 Registers Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 843 Window comparator for low power monitoring of input signals of conversion-result registers Figure 22-1 shows the block diagram of Precision ADC. The reference generation is located in the reference module (REF). SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 844: Precision Adc Block Diagram
(ADC14RDYIFG = 1). When an internal reference is not used (ADC14VRSEL != 0001 nor 1111), SHI_EN = 1. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 845 The application must ensure that the clock chosen for ADC14CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation does not complete and any result is invalid. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 846: Analog Multiplexer
Precision ADC supports 8-, 10-, 12-, and 14-bit resolution settings selected through the ADC14RES bits in the ADC14CTL1 register. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 847: Extended Sample Mode In 14-Bit Mode
Note: If internal ADC reference buffers are used, the SHI signal is gated while ADC14RDYIFG = 0. Figure 22-3. Extended Sample Mode in 14-Bit Mode SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 848: Pulse Sample Mode In 14-Bit Mode
LSB of the source voltage V for an accurate n-bit conversion, where n is the bits of resolution required. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 849: Analog Input Equivalent Circuit
ADC14MCTLx in a sequence when each conversion completes. The sequence continues until an ADC14EOS bit in ADC14MCTLx is processed; this is the last control byte processed. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 850: Precision Adc Conversion Result Formats
Repeat-single-channel A single channel is converted repeatedly. Section 22.2.8.3 Repeat-sequence-of-channels A sequence of channels is converted repeatedly. Section 22.2.8.4 (repeated autoscan) Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 851: Single-Channel Single-Conversion Mode
Result Stored Into ADC14MEMx, ADC14IFG.x is Set x = pointer to ADC14MCTLx Conversion result is unpredictable. Figure 22-7. Single-Channel Single-Conversion Mode SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 852: Sequence-Of-Channels Mode
ADC14EOS.x = 0 Conversion Completed, Result Stored Into ADC14MEMx, ADC14IFG.x is Set x = pointer to ADC14MCTLx Figure 22-8. Sequence-of-Channels Mode Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 853: Repeat-Single-Channel Mode
ADC14ENC = 1 Conversion Completed, Result Stored Into ADC14MEMx, ADC14IFG.x is Set x = pointer to ADC14MCTLx Figure 22-9. Repeat-Single-Channel Mode SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 854: Repeat-Sequence-Of-Channels Mode
ADC14EOS.x = 0) Conversion Completed, Result Stored Into ADC14MEMx, ADC14IFG.x is Set x = pointer to ADC14MCTLx Figure 22-10. Repeat-Sequence-of-Channels Mode Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 855 ADC14HIx must be written as signed binary (2s complement). Changing the ADC14DF bit or the ADC14RES bits reset the threshold registers. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 856: Typical Temperature Sensor Transfer Function
ADC channel. Ambient Temperature (° C) D020 Figure 22-11. Typical Temperature Sensor Transfer Function Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 857: Precision Adc Grounding And Noise Considerations
Using an External Positive Reference µ 50 nF VeREF- Connection to onboard ground Figure 22-12. Precision ADC Grounding and Noise Considerations SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 858 ADC14IV register, the ADC14OV interrupt condition is reset automatically. After the ADC14OV interrupt service is completed, the ADC14IFG3 generates another interrupt. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 859: 22.3 Adc14 Registers
(8-bit) accesses. For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 860: Adc14Ctl0 Register
ADC14SC bit gets reset to 0 automatically at the end of conversion and if ADC14ISSH = 1, the 1->0 transition on ADC14SC triggers another conversion. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 861: Adc14Ctl0 Register Description
SAMPCON signal duration, which is driven by the SHI signal (see Figure 22-3). See the device-specific data sheet for minimum sampling time. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 862 ADC14SC and ADC14ENC may be set together with one instruction. ADC14SC is reset automatically. 0b = No sample-and-conversion-start 1b = Start sample-and-conversion Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 863: Adc14Ctl1 Register
The value of CSTARTADDx is 0h to 1Fh, corresponding to ADC14MEM0 to ADC14MEM31 15-6 Reserved Reserved. Always reads as 0. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 864: Adc14Ctl1 Register Description
10b = Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample rate must not exceed 200 ksps. 11b = Reserved Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 865: Adc14Lo0 Register
14-bit mode, bits 3-0 are 0 in 12-bit mode, bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8-bit mode. The reset value is: 8000h SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 866: Adc14Hi0 Register
7-0 are 0 in 8-bit mode. The reset value is: 7FFCh (14 bit), 7FF0h (12 bit), 7FC0h (10 bit), or 7F00h (8 bit) Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 867: Adc14Lo1 Register
14-bit mode, bits 3-0 are 0 in 12-bit mode, bits 5-0 are 0 in 10-bit mode, and bits 7-0 are 0 in 8-bit mode. The reset value is: 8000h SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 868: Adc14Hi1 Register
7-0 are 0 in 8-bit mode. The reset value is: 7FFCh (14 bit), 7FF0h (12 bit), 7FC0h (10 bit), or 7F00h (8 bit) Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 869: Adc14Mctl0 To Adc14Mctl31 Register
Can be modified only when ADC14ENC = 0. 0b = Not end of sequence 1b = End of sequence Reserved Reserved. Always reads as 0. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 870 11110b = If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 11111b = If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 871: Adc14Mem0 To Adc14Mem31 Register
Reading this register clears the corresponding bit in ADC14IFG0. NOTE: ADC14MEMx register read by debugger does not clear the corresponding interrupt flag in ADC14IFG0 register. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 872: Adc14Ier0 Register
ADC14IE24 Interrupt enable. Enables or disables the interrupt request for the ADC14IFG24 bit. 0b = Interrupt disabled 1b = Interrupt enabled Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 873 ADC14IE11 Interrupt enable. Enables or disables the interrupt request for the ADC14IFG11 bit. 0b = Interrupt disabled 1b = Interrupt enabled SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 874 ADC14IE0 Interrupt enable. Enables or disables the interrupt request for the ADC14IFG0 bit. 0b = Interrupt disabled 1b = Interrupt enabled Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 875: Adc14Ier1 Register
ADC14LO threshold and below the ADC14HI threshold. 0b = Interrupt disabled 1b = Interrupt enabled Reserved Reserved. Always reads as 0. SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 876: Adc14Ifgr0 Register
ADC14CLRIFGR0 register is set to 1. 0b = No interrupt pending 1b = Interrupt pending Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 877: Adc14Ifgr0 Register Description
ADC14CLRIFGR0 register is set to 1. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 878 ADC14CLRIFGR0 register is set to 1. 0b = No interrupt pending 1b = Interrupt pending Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 879 ADC14CLRIFGR0 register is set to 1. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 880: Adc14Ifgr1 Register
0 by IV register read or when corresponding bit in ADC14CLRIFGR1 is set to 0b = No interrupt pending 1b = Interrupt pending Reserved Reserved. Always reads as 0. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 881: Adc14Clrifgr0 Register
0b = no effect 1b = clear pending interrupt flag CLRADC14IFG23 clear ADC14IFG23 0b = no effect 1b = clear pending interrupt flag SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 882: Adc14Clrifgr0 Register Description
0b = no effect 1b = clear pending interrupt flag CLRADC14IFG7 clear ADC14IFG7 0b = no effect 1b = clear pending interrupt flag Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 883 0b = no effect 1b = clear pending interrupt flag CLRADC14IFG0 clear ADC14IFG0 0b = no effect 1b = clear pending interrupt flag SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 884: Adc14Clrifgr1 Register
1b = clear pending interrupt flag CLRADC14INIFG clear ADC14INIFG 0b = no effect 1b = clear pending interrupt flag Reserved Reserved. Always reads as 0. Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 885: Adc14Iv Register
ADC14IVx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 ADC14IVx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 SLAU356I – March 2015 – Revised June 2019 Precision ADC Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 886: Adc14Iv Register Description
4Ah = Interrupt Source: ADC14MEM31 interrupt flag; Interrupt Flag: ADC14IFG31 4Ch = Interrupt Source: ADC14RDYIFG interrupt flag; Interrupt Flag: ADC14RDYIFG; Priority: Lowest Precision ADC SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 887 This chapter describes the Comparator_E..........................Topic Page ..................23.1 COMP_E Introduction ................... 23.2 COMP_E Operation ................... 23.3 COMP_E Registers SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 888: Comp_E Block Diagram
CEIMSEL COUT 0000 CERSEL CEOUTPOL 0001 Reference Voltage from shared Generator reference 1110 1111 Figure 23-1. COMP_E Block Diagram Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 889 The CESHORT bit shorts the Comparator_E inputs. This can be used to build a simple sample-and-hold for the comparator (see Figure 23-2). SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 890: Comp_E Sample-And-Hold
Selecting the output filter can reduce errors associated with comparator oscillation. Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 891: Rc-Filter Response At The Output Of The Comparator
It is recommended to set CEREFLx = 00 prior to changing the CEREFLx settings. SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 892: Transfer Characteristic And Power Dissipation In A Cmos Inverter/Buffer
(see Figure 23-6). A reference resistor Rref is compared to Rmeas. Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 893: Temperature Measurement System
Equation SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 894 æ ö ref1 ç ÷ × C × ln ç ÷ è ø meas meas meas × meas (13) Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 895 For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 896: Cexctl0 Register
Reserved. Always reads as 0. CEIPSEL Channel input selected for the V+ terminal of the comparator if CEIPEN is set to Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 897: Cexctl1 Register
Output value. This bit reflects the value of the Comparator output. Writing this bit has no effect on the comparator output. SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 898: Cexctl2 Register
VREF is applied to the V+ terminal CEREF0 Reference resistor tap 0. This register defines the tap of the resistor string while CEOUT = 0. Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 899: Cexctl3 Register
Comparator_E. The bit CEPD8 disables the port of the comparator channel 8. 0b = The input buffer is enabled. 1b = The input buffer is disabled. SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 900 Comparator_E. The bit CEPD0 disables the port of the comparator channel 0. 0b = The input buffer is enabled. 1b = The input buffer is disabled. Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 901: Cexint Register
Comparator output interrupt flag. The bit CEIES defines the transition of the output setting this bit. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Comparator E Module (COMP_E) Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 902: Cexiv Register
06h = Reserved 08h = Reserved 0Ah = Interrupt Source: Comparator ready interrupt; Interrupt Flag: CERDYIFG; Interrupt Priority: Lowest Comparator E Module (COMP_E) SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 903 Introduction – UART Mode ..............24.3 eUSCI_A Operation – UART Mode .................. 24.4 eUSCI_A UART Registers SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 904 Independent interrupt capability for receive, transmit, start bit received, and transmit complete Figure 24-1 shows the eUSCI_Ax when configured for UART mode. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 905: Eusci_Ax Block Diagram - Uart Mode (Ucsync = 0)
UCTXADDR UCMODEx UCSPB Figure 24-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 906: Character Format
In idle-line multiprocessor format, this bit is set when a received character is an address. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 907: Idle-Line Format
The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data is misinterpreted as an address. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 908: Address-Bit Multiprocessor Format
(UCTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 909: Auto Baud-Rate Detection - Break/Synch Sequence
The latter case can be discovered by checking the received data and the UCFE bit. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 910: Uart Vs Irda Data Format
= Wake time from any low-power mode. Zero when the device is in active mode. WAKE Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 911: Receive Error Conditions
UCAxRXBUF to detect this condition. Note that, in this case, the UCRXERR flag is not set. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 912: Glitch Suppression, Eusci_A Receive Not Started
If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud-rate generator is turned off. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 913: Bitclk Baud-Rate Timing With Ucos16
⋮ 0x35 0x36 0x37 ⋮ 0xFF Section 24.3.10 describes the correct setting of UCBRSx. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 914: Bitclk16 Modulation Pattern
Table 24-3. BITCLK16 Modulation Pattern Number of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 915 However it is also possible to look up the correct settings in table with typical crystals (see Table 24-5). SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 916 –0.5 BRCLK cycles and +0.5 BRCLK cycles, independent of the SYNC selected baud-rate generation mode. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 917: Receive Error
(see the device-specific data sheet). SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 918: Brclk /Baud Rate
Assumes a stable clock source for BRCLK with negligible jitter (for example, from a crystal oscillator). Any frequency variation or jitter of the clock source will make the errors worse. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 919 An interrupt request is generated if UCTXIE is set. UCTXIFG is automatically reset if a character is written to UCAxTXBUF. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 920: Uart State Change Interrupt Flags
// Vector 6: UCSTTIFG break; case 0x08: ... // Vector 8: UCTXCPTIFG break; default: break; Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 921 (UCRXERR, UCFE, UCPE, UCOE, and UCBRK) are cleared after the read. Thus these errors might go unnoticed. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 922: 24.4 Eusci_A Uart Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 923: Ucaxctlw0 Register
0b = Received break characters do not set UCRXIFG. 1b = Received break characters set UCRXIFG. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 924: Ucaxctlw1 Register
01b = Approximately 20 ns 10b = Approximately 30 ns 11b = Approximately 50 ns Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 925: Ucaxbrw Register
Baud-Rate Generation" section shows the modulation pattern. Reserved Reserved UCOS16 Oversampling mode enabled 0b = Disabled 1b = Enabled SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 926: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI_A inactive 1b = eUSCI_A transmitting or receiving Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 927: Ucaxrxbuf Register
UCTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 928: Ucaxabctl Register
1b = Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly. Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 929: Ucaxirctl Register
IrDA encoder and decoder enable 0b = IrDA encoder/decoder disabled 1b = IrDA encoder/decoder enabled SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 930: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 931: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCAxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 932: Ucaxiv Register
06h = Interrupt Source: Start bit received; Interrupt Flag: UCSTTIFG 08h = Interrupt Source: Transmit complete; Interrupt Flag: UCTXCPTIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 933 Operation – SPI Mode ..................25.4 eUSCI_A SPI Registers ..................25.5 eUSCI_B SPI Registers SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 934 Independent interrupt capability for receive and transmit Figure 25-1 shows the eUSCI when configured for SPI mode. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 935: Eusci Block Diagram - Spi Mode
Set UCFE Transmit State Machine Set UCxTXIFG Figure 25-1. eUSCI Block Diagram – SPI Mode SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 936: Ucxste Operation
Initialize all eUSCI registers with UCSWRST = 1 (including UCxCTL1). Configure ports. Clear UCSWRST through software. Enable interrupts (optional) with UCRXIE or UCTXIE. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 937: Character Format
The fourth pin is used as output to generate a slave enable signal (UCSTEM = 1). The bit UCSTEM is used to select the corresponding mode. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 938: Slave Mode
Receive Shift Register SCLK UCxCLK Common SPI MSP432 USCI Figure 25-3. eUSCI Slave and External Master Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 939: Spi Enable
The polarity and phase of UCxCLK are independently configured with the UCCKPL and UCCKPH control bits of the eUSCI. Figure 25-4 shows the timing for each case. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 940: Using The Spi Mode With Low-Power Modes
UCRXIE is set. UCRXIFG and UCRXIE are reset by a Hard Reset or when UCSWRST = 1. UCRXIFG is automatically reset when UCxRXBUF is read. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 941 SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 942: Eusci_A Spi Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 943: Ucaxctlw0 Register
0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 944: Ucaxbrw Register
Table 25-4. UCAxBRW Register Description Field Type Reset Description 15-0 UCBRx Bit clock prescaler setting Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 945: Ucaxstatw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 946: Ucaxrxbuf Register
UCRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 947: Ucaxtxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 948: Ucaxie Register
1b = Interrupt enabled UCRXIE Receive interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 949: Ucaxifg Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 950: Ucaxiv Register Description
Priority: Highest 004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 951: Ucaxiv Register 25.5 Eusci_B Spi Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 952: Ucbxctlw0 Register
0b = Disabled. eUSCI reset released for operation. 1b = Enabled. eUSCI logic held in reset state. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 953: Ucbxbrw Register
This bit indicates if a transmit or receive operation is in progress. 0b = eUSCI inactive 1b = eUSCI transmitting or receiving SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 954: Ucbxrxbuf Register
UCTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 955: Ucbxie Register
Receive interrupt flag. UCRXIFG is set when UCxxRXBUF has received a complete character. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 956: Ucbxiv Register
Priority: Highest 0004h = Interrupt Source: Transmit buffer empty; Interrupt Flag: UCTXIFG; Interrupt Priority: Lowest Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 957: Mode
................26.3 eUSCI_B Operation – I C Mode ..................26.4 eUSCI_B I2C Registers SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 958: Enhanced Universal Serial Communication Interface B (Eusci_B) Overview
Clock low time-out interrupt to avoid bus stalls Figure 26-1 shows the eUSCI_B when configured in I C mode. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 959: Mode
SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 960: Eusci_B Initialization And Reset
SCL clock. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 961: Addressing Modes
10-bit addressing mode with the eUSCI_B module. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 962: Module 10-Bit Addressing Format
Bits set or reset by software Bits set or reset by hardware Figure 26-8. I C Time-Line Legend SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 963: Slave Transmitter Mode
C state machine returns to its address-reception state. Figure 26-9 shows the slave transmitter operation. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 964: C Slave Receiver Mode
To avoid loss of data, the UCBxRXBUF must be read before UCTXNACK is set. When the master generates a STOP condition, the UCSTPIFG flag is set. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 965: C Slave 10-Bit Addressing Mode
This sets the UCSTTIFG flag if it was previously cleared by software, and the eUSCI_B modules switches to transmitter mode with UCTR = 1. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 966 SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 967: C Master Transmitter Mode
START, it must be written into UCBxTXBUF again. Any set UCTXSTT or UCTXSTP is also discarded. Figure 26-12 shows the I C master transmitter operation. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 968 (UCGC=1 if general call) USCI continues as Slave Receiver Figure 26-12. I C Master Transmitter Mode SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 969: I 2 C Master Receiver Mode
C transaction is initiated with setting UCTXSTT = 1. Otherwise, the current transaction might be affected. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 970 UCTXIFG = 1 USCI continues as Slave Transmitter Figure 26-13. I C Master Receiver Mode SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 971: Arbitration Procedure Between Two Master Transmitters
Master 1 sends a repeated START condition and master 2 sends a STOP condition. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 972: C Module Operating Modes 26.3.5 Glitch Filtering
• eUSCI_B is acting as master and a connected slave drives SCL low. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 973: C Clock Generation And Synchronization 26.3.7 Byte Counter
Otherwise, the application must have enough processor bandwidth to ensure that the UCBCNT interrupt routine is executed in time to generate, for example, a RESTART. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 974: Multiple Slave Addresses
If the user decides not to acknowledge the address, the TXIFG also must be reset. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 975: Mode With Low-Power Modes
C State Change Interrupt Operation Table 26-2 describes the I C state change interrupt flags. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 976 Write access of the UCBxIV register clears all pending Interrupt conditions and flags. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 977: 26.4 Eusci_B I2C Registers
For details on the register bit access and reset conventions that are used in the following sections, refer to Preface. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 978: 26.4.1 Ucbxctlw0 Register
0b = Do not acknowledge the slave address 1b = Acknowledge the slave address SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 979 0b = Disabled. eUSCI_B released for operation. 1b = Enabled. eUSCI_B logic held in reset state. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 980: 26.4.2 Ucbxctlw1 Register
UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold. 11b = Reserved SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 981 00b = 50 ns 01b = 25 ns 10b = 12.5 ns 11b = 6.25 ns SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 982: 26.4.3 Ucbxbrw Register
UCBBUSY Bus busy 0b = Bus inactive 1b = Bus busy Reserved Reserved SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 983: 26.4.5 Ucbxtbcnt Register
UCASTPx is different from 00. Modify only when UCSWRST = 1. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 984: 26.4.6 Ucbxrxbuf Register
Writing to the transmit data buffer clears the UCTXIFGx flags. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 985: 26.4.8 Ucbxi2Coa0 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 986: 26.4.9 Ucbxi2Coa1 Register
MSB and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. Modify only when UCSWRST = 1. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 987: 26.4.11 Ucbxi2Coa3 Register
SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 988: 26.4.13 Ucbxaddmask Register
MSB and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB. SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 989: 26.4.15 Ucbxie Register
UCSTPIE STOP condition interrupt enable 0b = Interrupt disabled 1b = Interrupt enabled SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 990 UCRXIE0 Receive interrupt enable 0 0b = Interrupt disabled 1b = Interrupt enabled SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 991: 26.4.16 Ucbxifg Register
(see the Byte Counter Interrupt section). 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 992 UCBxI2COA0 was on the bus in the same frame. 0b = No interrupt pending 1b = Interrupt pending SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 993: 26.4.17 Ucbxiv Register
1Ch = Interrupt Source: Clock low timeout; Interrupt Flag: UCCLTOIFG 1Eh = Interrupt Source: 9th bit position; Interrupt Flag: UCBIT9IFG; Priority: Lowest SLAU356I – March 2015 – Revised June 2019 Enhanced Universal Serial Communication Interface (eUSCI) – I C Mode Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 994: Lcd_F Controller
........................... Topic Page ................27.1 LCD_F Controller Introduction ............27.2 LCD_F Controller Architecture and Operation ..................... 27.3 LCD_F Registers 1015 LCD_F Controller SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 995: 27.1 Lcd_F Controller Introduction
Up to 4 × 50 or 8 × 46 Up to 4 × 60 or 8 × 56 (device and package specific) Charge pump Present Present Present Absent SLAU356I – March 2015 – Revised June 2019 LCD_F Controller Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 996: 27.1.3 Functional Block Diagram
V1 V2 V3 V4 V5 LFXTCLK LCD Bias Generator LCDPREx LCDDIVx LCDMXx LCDREXT LCDEXTBIAS LCD2B R03EXT Figure 27-1. LCD_F Controller Block Diagram LCD_F Controller SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 997: 27.2 Lcd_F Controller Architecture And Operation
LCDBLKMODx = 11. It is automatically cleared when a LCD or blinking memory register is written. SLAU356I – March 2015 – Revised June 2019 LCD_F Controller Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 998: 27.2.4 Memory
6-mux: up to 252 segments (6 COM lines) • 7-mux: up to 287 segments (7 COM lines) • 8-mux: up to 320 segments (8 COM lines) LCD_F Controller SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 999: 27.2.5 Lcd_F Functional Operation
When LCDCSSx = 1, the content of LCDMx defines which common line (COM0 to COM7) is used at corresponding LCD pin Lx. The following sections describes the use of this functionality. SLAU356I – March 2015 – Revised June 2019 LCD_F Controller Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...
Page 1000: Lcdmx Com Assignment
When LCDSON = 0, each LCD segment is off. The LCD timing generator and interrupts continue to work as programmed even when the LCD segments are off due to LCDSON = 0. 1000 LCD_F Controller SLAU356I – March 2015 – Revised June 2019 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated...

Texas Instruments SimpleLink MSP432P4 Series Technical Reference Manual

Msp432P4Xx Simplelink™ Microcontrollers Technical Reference Manual

Preface

1 Cortex-M4F Processor

2 Cortex-M4F Peripherals

Quick Links

Chapters

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Summary of Contents for Texas Instruments SimpleLink MSP432P4 Series