Table of Contents

Advertisement

Quick Links

MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 400 µA at 1 MHz, 2.2 V
– Standby Mode: 1.3 µA
– Off Mode (RAM Retention): 0.22 µA
• Five Power-Saving Modes
• Wakeup From Standby Mode in Less Than 6 µs
• 16-Bit RISC Architecture, Extended Memory,
125‑ns Instruction Cycle Time
• Three-Channel Internal DMA
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold and
Autoscan Feature
• Three Configurable Operational Amplifiers
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• 16-Bit Timer_A With Three Capture/Compare
Registers
• 16-Bit Timer_B With Seven Capture/Compare-
With-Shadow Registers
• On-Chip Comparator
• Supply Voltage Supervisor and Monitor With
Programmable Level Detection
• Serial Communication Interface (USART1), Select
Asynchronous UART or Synchronous SPI by
Software
1.2
Applications
Portable Medical Applications
1.3
Description
The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-
power modes to active mode in less than 6 µs.
The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance
12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge
pump.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
Tools &
Technical
Software
Documents
• Universal Serial Communication Interface
– Enhanced UART Supports Automatic Baud-
Rate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
2
– I
C
• Serial Onboard Programming, Programmable
Code Protection by Security Fuse
• Brownout Detector
• Basic Timer With Real-Time Clock (RTC) Feature
• Integrated LCD Driver up to 160 Segments With
Regulated Charge Pump
Section 3
Summarizes the Available Family
Members
– MSP430FG4616, MSP430FG4616
92KB+256B of Flash or ROM
4KB of RAM
– MSP430FG4617, MSP430CG4617
92KB+256B of Flash or ROM
8KB of RAM
– MSP430FG4618, MSP430CG4618
116KB+256B of Flash or ROM
8KB of RAM
– MSP430FG4619, MSP430CG4619
120KB+256B of Flash or ROM
4KB of RAM
• For Complete Module Descriptions, see the
MSP430x4xx Family User's Guide (SLAU056)
E-Meter Applications
Support &
Reference
Community
Design
SLAS508J – APRIL 2006 – REVISED JUNE 2015

Advertisement

Table of Contents
loading

Summary of Contents for Texas Instruments MSP430FG461x series

  • Page 1 Sample & Support & Reference Product Tools & Technical Community Design Folder Software Documents MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616 SLAS508J – APRIL 2006 – REVISED JUNE 2015 MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers 1 Device Overview Features • Low Supply-Voltage Range: 1.8 V to 3.6 V •...
  • Page 2 SVS/ SVM 15/16-Bit Registers Shadow MAC, 1, 2,3,4 Mux SPI, I2 C MACS RST/NMI Figure 1-1. Functional Block Diagram Device Overview Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 3: Table Of Contents

    5.28 12-Bit ADC, External Reference Mechanical, Packaging, and Orderable ...... 5.29 12-Bit ADC, Built-In Reference ..........Information Table of Contents Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 4 • Added Section 7 and moved Trademarks and ESD Caution sections to it ........................• Added Section 8 Revision History Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 5: Device Comparison

    Section 8, or see the TI website at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Device Comparison Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 6: Terminal Configuration And Functions

    P5.4/COM3 P9.7/S10 P5.3/COM2 P9.6/S11 P5.2/COM1 P9.5/S12 COM0 P9.4/S13 P4.2/STE1/S39 Figure 4-1. 100-Pin PZ Package (Top View) Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 7 The shortest ground return path to the device should be established to ball location B3, DV Figure 4-2. 113-Pin ZQW Package (Top View) Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 8: Signal Descriptions

    LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0, VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal. Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 9 P8.0 General-purpose digital I/O LCD segment output 25 P7.7 General-purpose digital I/O LCD segment output 26 Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 10 Common output, COM3 for LCD backplanes P5.5 General-purpose digital I/O Input port of lowest analog LCD level (V5) Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 11 Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output P2.1 General-purpose digital I/O Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 12 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1. Do not power up before powering DV and DV Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 13 The shortest ground return path to the device should be established to ball location J4, J9, B3, DV L2, L11, M1, M12 Terminal Configuration and Functions Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 14: Specifications

    (3) In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 15 4.6 MHz 3.0 MHz Supply Voltage (V) Figure 5-1. Frequency vs Supply Voltage Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 16: Excluding External Current

    Current consumption of active mode versus supply voltage, FG version: + 200 µA/V × (V – 3 V) (AM) (AM) [3 V] Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 17: Thermal Characteristics

    (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 18: Schmitt-Trigger Inputs - Ports P1 To P10, Rst/Nmi, Jtag (Tck, Tms, Tdi/Tclk,Tdo/Tdi)

    , for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified OH(max) OL(max) voltage drop. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 19: Output Frequency

    50% – 50% + = 20 pF, V = 2.2 V, 3 V (SMCLK) (DCOCLK) 15 ns 15 ns Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 20: Typical Characteristics - Outputs

    Figure 5-4. Typical High-Level Output Current vs Typical High- Figure 5-5. Typical High-Level Output Current vs Typical High- Level Output Current Level Output Current Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 21: Wake-Up Timing From Lpm3

    LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0, VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 22: Comparator_A

    (2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 23: Typical Characteristics - Comparator_A

    » µ Figure 5-8. Block Diagram of Comparator_A Module VCAOUT Overdrive 400 mV t(response) Figure 5-9. Overdrive Definition Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 24: Por, Bor

    - Pulse Width - Figure 5-11. V Level with a Square Voltage Drop to Generate a POR or BOR Signal CC(drop) Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 25: Svs (Supply Voltage Supervisor And Monitor)

    (2) The recommended operating voltage range is limited to 3.6 V. (3) The current consumption of the SVS module is not included in the I current consumption data. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 26 Figure 5-14. V with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal CC(drop) Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 27: Dco

    (DCO) (DCO) (DCO20 C) (DCO3V) ° ° Figure 5-15. DCO Frequency vs Supply Voltage V and vs Ambient Temperature Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 28 FN_4=0 FN_4=0 FN_4=1 FN_4=x FN_8=0 FN_8=0 FN_8=0 FN_8=0 FN_8=1 Figure 5-17. Five Overlapping DCO Ranges Controlled by FN_x Bits Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 29: Crystal Oscillator, Lfxt1 Oscillator

    (1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 30: Usci (Spi Master Mode)

    SIMO input data hold time HD,SI 2.2 V SOMI output data valid time UCLK edge to SOMI valid, C = 20 pF VALID,SO Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 31 LOW /HIGH HD ,MI SU ,MI SO MI VALID ,MO SI MO Figure 5-19. SPI Master Mode, CKPH = 1 Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 32 LOW /HIGH HD ,SI SU ,SI SI MO VALID ,SO SO MI Figure 5-21. SPI Slave Mode, CKPH = 1 Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 33: Usci (I C Mode)

    The deglitch circuitry is active only on negative transitions on the URXD1 line. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 34: 12-Bit Adc, Power Supply And Input Range Conditions

    (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 35: 12-Bit Adc, Built-In Reference

    100 ms REFON Figure 5-23. Typical Settling Time of Internal Reference t vs External Capacitor on V REFON REF+ Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 36 Switched to AV Figure 5-25. Supply Voltage and Reference Voltage Design V = AV , Internally Connected REF– REF– Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 37: 12-Bit Adc, Timing Parameters

    REF+ REF– REF– 2.2 V, 3 V ±2 ±5 error CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 38: 12-Bit Adc, Temperature Sensor And Built-In

    (3) PSRR = 20 × log{ΔAV /ΔV DAC12_xOUT (4) V is applied externally. The internal reference is not used. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 39: 12-Bit Dac, Linearity Specifications

    C Load = 100pF Positive Negative DAC Code Figure 5-26. Linearity Test Load Conditions and Gain and Offset Definition Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 40 1536 2048 2560 3072 3584 4095 DAC12_xDAT - Digital Code Figure 5-28. Typical DNL Error vs Digital Input Data Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 41: 12-Bit Dac, Output Specifications

    (5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 42: 12-Bit Dac, Dynamic Specifications

    Figure 5-30. Settling Time and Glitch Energy Testing Conversion 1 Conversion 2 Conversion 3 V OUT t SRLH t SRHL Figure 5-31. Slew Rate Testing Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 43: 12-Bit Dac, Dynamic Specifications Continued

    I Load V DAC12_xOUT AV CC DAC12_1 DAC1 Toggle C Load = 100 pF Figure 5-33. Crosstalk Test Conditions Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 44: Operational Amplifier Oa, Supply Specifications

    (2) The input bias current is overridden by the input leakage current. (3) Calculated using the box method. (4) Specification valid for voltage-follower OAx configuration. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 45: Operational Amplifier Oa, Dynamic Specifications

    Input Frequency - kHz Input Frequency - kHz Figure 5-35. Typical Open-Loop Gain vs Frequency Figure 5-36. Typical Phase vs Frequency Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 46: Operational Amplifier Oa Feedback Network, Noninverting Amplifier Mode (Oafcx = 4)

    (2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 47: Flash Memory (Fg461X Devices Only)

    (1) After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. Specifications Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 48: Detailed Description

    General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 49: Instruction Set

    R10 + 2→ R10 Immediate • MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) NOTE: S = source D = destination Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 50: Operating Modes

    – MCLK, FLL+ loop control, and DCOCLK are disabled – DCO DC generator is disabled – Crystal oscillator is stopped Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 51: Interrupt Vector Addresses

    (5) The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if necessary. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 52: Special Function Registers (Sfrs)

    USART1 UART and SPI receive-interrupt enable UTXIE1 USART1 UART and SPI transmit-interrupt enable BTIE Basic timer interrupt enable Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 53 USART1: UART mode receive enable UTXE1 USART1: UART mode transmit enable USPIE1 USART1: SPI mode transmit and receive enable Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 54: Memory Organization

    16 bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 01FFh-0100h 8 bit 0FFh-010h 0FFh-010h 0FFh-010h 0FFh-010h 8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h 0Fh-00h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 55: Bootstrap Loader (Bsl)

    CPU to remain in sleep mode without having to awaken to move data to or from a peripheral. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 56 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 57 85/D7 - P1.2 CAOUT (internal) CCI1B ADC12 (internal) CCR1 79/A10 - P2.0 CCI2A 79/A10 - P2.0 ACLK (internal) CCI2B CCR2 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 58 65/F11 - P3.6 65/F11 - P3.6 CCI5B CCR5 64/F12 - P3.7 CCI6A 64/F12 - P3.7 ACLK (internal) CCI6B CCR6 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 59 14 - P10.7 OA2I1 OA2I1 OA2O 14 - P10.7 DAC12_0OUT OA2OUT DAC12_0OUT OA2O ADC12 (internal) (internal) DAC12_1OUT DAC12_1OUT (internal) Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 60 DMA channel 2 source address DMA2SA 01EAh DMA channel 2 destination address DMA2DA 01EEh DMA channel 2 transfer size DMA2SZ 01F2h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 61 Port PB selection PBSEL 00Eh Port PB direction PBDIR 00Ch Port PB output PBOUT 00Ah Port PB input PBIN 008h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 62 UCAABCTL 05Dh Comparator_A Comparator_A port disable CAPD 05Bh Comparator_A control 2 CACTL2 05Ah Comparator_A control 1 CACTL1 059h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 63 Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 64 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 001h SFR interrupt enable 1 000h Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 65: Input/Output Schematics

    P 1IE.x P1IRQ .x P1IFG .x Interrupt P1SEL.x Edge P 1IES .x Select Note : x = 0,1, 2,3,4,5 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 66 P1.4/TBCLK/SMCLK P1.4 (I/O) I: 0; O: 1 Timer_B7.TBCLK SMCLK P1.5/TACLK/ACLK P1.5 (I/O) I: 0; O: 1 Timer_A3.TACLK ACLK Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 67 P1.6 (I/O) I: 0; O: 1 P1.7/CA1 P1.7 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 68 P 2IE .x P2IRQ .x P2IFG .x Interrupt P2SEL.x Edge P 2IES .x Select Note : x = 0,1,2,3,6,7 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 69 I: 0; O: 1 ADC12CLK DMAE0 (1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 70 USCI_A0.UCA0RXD (1) X = don't care (2) When in USCI mode, P2.4 is set to output, P2.5 is set to input. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 71 (3) If the I C functionality is selected the output drives only the logical 0 to V level. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 72 I: 0; O: 1 Timer_B7.CCI6A and Timer_B7.CCI6B Timer_B7.TB6 (1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 73 USART1.URXD1 (1) X = don't care (2) When in USART1 mode, P4.0 is set to output, P4.1 is set to input. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 74 I: 0; O: 1 P4.5/SOMI/S36 USART1.UCLK1 (1) X = don't care (2) The pin direction is controlled by the USART1 module. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 75 USCI_A0.UCA0RXD (1) X = don't care (2) When in USCI mode, P4.6 is set to output, P4.7 is set to input. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 76 (2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 77 0 if DAC12.1AMPx = 0 and DAC 12.1OPS = 1 1 if DAC12.1AMPx = 1 and DAC 12.1OPS = 1 2 if DAC12.1AMPx > 1 and DAC 12.1OPS = 1 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 78 (2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 79 I: 0; O: 1 COM2 P5.4/COM3 P5.4 (I/O) I: 0; O: 1 COM3 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 80 (1) X = don't care (2) External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 81 (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 82 (3) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 83 1 if DAC 12.0AMPx = 1 and DAC 12.0OPS = 0 2 if DAC 12.0AMPx > 1 and DAC 12.0OPS = 0 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 84 (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 85 1 if DAC 12.1AMPx = 1 and DAC 12.1OPS = 0 2 if DAC 12.1AMPx > 1 and DAC 12.1OPS = 0 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 86 (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 87 P7.0/UCA0STE /S33 P7IN.x Module X IN Note: x = 0, 1, 2, 3 y = 30, 31, 32, 33 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 88 I: 0; O: 1 USCI_A0.UCA0CLK (1) X = don't care (2) The pin direction is controlled by the USCI module. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 89 P7.6 (I/O) I: 0; O: 1 P7.7/S26 P7.7 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 90 P8.4 (I/O) I: 0; O: 1 P8.5/S23 P8.5 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 91 P8.6 (I/O) I: 0; O: 1 P8.7/S25 P8.7 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 92 P9.4 (I/O) I: 0; O: 1 P9.5/S12 P9.5 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 93 P9.6 (I/O) I: 0; O: 1 P9.7/S10 P9.7 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 94 P10.4 (I/O) I: 0; O: 1 P10.5/S4 P10.5 (I/O) I: 0; O: 1 (1) X = don't care Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 95 (2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 96 (2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 97 /DAC0 , unpredictable voltage levels will be on pin. REF+ In this situation, the DAC0 output is fed back to its own reference input. Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 98 Burn and Test Fuse TDI/TCLK Test DV CC Emulation Module DV CC RST/NMI Tau ~ 50 ns Brownout Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 99 (default condition). The JTAG pins are terminated internally and therefore do not require external termination. Time TMS Goes Low After POR I(TF) ITDI/TCLK Figure 6-1. Fuse Check Mode Current Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 100: Device And Documentation Support

    Software development tools are available from TI or from third parties. Open source solutions are also available. This device is supported by Code Composer Studio™ IDE (CCS). Device and Documentation Support Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619...
  • Page 101 (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend for reading the complete device name for any family member. Device and Documentation Support Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 102 -HT = Extreme Temperature Parts ( 55°C to 150°C) – -Q1 = Automotive Q100 Qualified Figure 7-1. Device Nomenclature Device and Documentation Support Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 103: Documentation Support

    Click here Click here Click here MSP430CG4616 Click here Click here Click here Click here Click here Device and Documentation Support Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616...
  • Page 104: Glossary

    MSP430, MicroStar Junior, Code Composer Studio, E2E are trademarks of Texas Instruments. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 105 This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 106 PACKAGE OPTION ADDENDUM www.ti.com 31-May-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430FG4616IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG4616 &...
  • Page 107 PACKAGE OPTION ADDENDUM www.ti.com 31-May-2017 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430FG4619IZQW ACTIVE Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 M430FG4619 MICROSTAR &...
  • Page 108 PACKAGE OPTION ADDENDUM www.ti.com 31-May-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3...
  • Page 109 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430FG4616IPZR LQFP 1000 330.0 24.4 17.0 17.0 20.0 24.0 MSP430FG4616IZQWR BGA MI...
  • Page 110 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2017 Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) R JUNI MSP430FG4619IZQWT BGA MI 180.0 16.4 12.0 16.0 CROSTA R JUNI *All dimensions are nominal Device Package Type Package Drawing Pins...
  • Page 111 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2017 Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) JUNIOR MSP430FG4619IZQWT BGA MICROSTAR 213.0 191.0 55.0 JUNIOR Pack Materials-Page 3...
  • Page 113 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 115 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

Table of Contents