Overview; Purpose; Evm Basic Functions; Power Requirements - Texas Instruments DAC5687 EVM User Manual

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1

Overview

This user's guide document gives a general overview of the DAC5687 evaluation module (EVM) and
provides a general description of the features and functions to be considered while using this module.
1.1

Purpose

The DAC5687 EVM provides a platform for evaluating the DAC5687 digital-to-analog converter (DAC)
under various signal, reference, and supply conditions. This document should be used in combination with
the EVM schematic diagram supplied.
1.2

EVM Basic Functions

Digital inputs to the DAC can be provided with CMOS level signals up to 250 MSPS (external clock mode)
through two 34-pin headers. This enables the user to provide high-speed digital data to the DAC5687
device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design the
analog outputs of the DAC5687 device can be configured to drive a 50-Ω terminated cable using a 4:1 or
1:1 impedance ratio transformer, or single-ended referred to AVDD. The EVM also allows for an option to
double the output power by summing the DAC A and DAC B outputs through a 1:1 transformer.
The EVM allows the user to input single-ended, TTL/CMOS level signals, to generate differential clock
sources for both CLK1 and CLK2. See Section 4.1, Input Clocks, for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5687 device, options on the EVM allow
an external reference to be provided to the DAC.
The DAC5687 EVM allows the user to program the DAC5687 internal registers with the supplied computer
parallel port cable and serial interface software. The interface allows read and write access to all registers
that define the operation mode of the DAC5687 device.
1.3

Power Requirements

The demonstration board requires only two power supplies. 3.3 Vdc is required at banana jack J7, with the
return connected to J9. 1.8 Vdc is required at banana jack J8, with the return to J10.
1.3.1
Voltage Limits
Exceeding the maximum input voltages can damage EVM components.
Undervoltage may cause improper operation of some or all of the EVM
components.
SLWU017B – APRIL 2005 – Revised March 2007
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SLWU017B – APRIL 2005 – Revised March 2007
CAUTION
User's Guide
DAC5687 EVM
DAC5687 EVM
5

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