Table of Contents
Advertisement
Overview
1.4
Software Installation
All necessary software to operate the serial interface is provided on the enclosed CD-ROM.
1. Insert the CD-ROM into the computer to be used to operate the serial interface.
2. Click on the zipped directory called DAC5687SPI_Installv2p2.zip. Extract all of the files into a new
directory, called C:\temp, on the PC.
3. Go the following directory: C:\temp\Installer. Double click on the file called setup.exe.
4. The software will create a top level directory at the following location: C:\Program
Files\TI.fdr\DAC5687_SPI. This directory will contain the required files as well as a labwindows-cvi
runtime engine to run the software.
5. Once the installation is complete, the software is launched by running DAC5687_SPI.exe. See
Chapter 2, DAC5687 EVM Operational Procedure, for instructions on operating the serial interface
software.
1.5
Hardware Configuration
The DAC5687 EVM can be set up in a variety of configurations to accommodate a specific mode of
operation. Before starting evaluation, the user should decide on the configuration and make the
appropriate connections or changes. The demonstration board comes with the following factory-set
configuration:
• Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 and
J4.
• Transformer-coupled outputs using 4:1 transformers T1 and T2.
• The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.
• Full-scale output current set to 20 mA through RBIAS resistor R1.
• The DAC5687 output is enabled (sleep mode disabled).
• TxENABLE is set high to enable the DAC5687 device to process data. A jumper is installed between
pins 11 and 12 on J15.
• Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.
• Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To prepare the DAC5687 EVM for evaluation, connect the following:
1. 3.3 V to J7 and the return to J9.
2. 1.8 V to J8 and the return to J10.
3. Provide a single-ended, 1-V
PLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. A second
sine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 is used to
clock data into the DAC5687 and the signal on CLK2 is used to clock the internal DAC. CLK1 and
CLK2 must be phase-aligned for this option to work properly. In order to preserve the specified
performance of the DAC5687 converter, the clock sources must feature very low jitter. Using a clock
with a 50% duty cycle gives optimum dynamic performance.
4. Use a digital test pattern generator with 50-Ω outputs to provide 3.3-V CMOS logic level inputs to
connectors J13 and J14. Adjust the digital inputs to provide the proper voltage levels and setup and
hold times at the DAC5687 inputs. See the DAC5687 data sheet (SLWS164) for timing information.
5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the other
end of the cable to J1 on the EVM.
6. The DAC5687 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19
for IOUTB.
6
DAC5687 EVM
, 0-V offset sine-wave signal to SMA connector J3 (CLK1) if the internal
PP
SLWU017B – APRIL 2005 – Revised March 2007
Submit Documentation Feedback
www.ti.com
Advertisement
Table of Contents
