Circuit Description; Input Clocks; Input Data - Texas Instruments DAC5687 EVM User Manual

Circuit Description

Value
CDCV304
SN74HC241
SN74HCT14
Transformer
Transformer
Transformer
DB25F-RA
Switch
4 Circuit Description
This chapter describes the circit functions of the DAC5687 EVM.
4.1

Input Clocks

The initial configuration of this EVM provides transformer-coupled differential clocks from single-ended
input sources. With the EVM configured for PLL clock mode, a 1-V
square wave is applied to SMA connector J3 to be used as the data input rate clock. The signal is
converted to a differential clock by transformer T3 and provides the CLK1 and CLK1C inputs to the
DAC5687 device. This input represents a 50-Ω load to the source. In order to preserve the specified
performance of the DAC5687 converter, the clock source should feature very low jitter. Using a clock with
a 50% duty cycle gives optimum dynamic performance.
With the EVM configured for external clock mode, a 1-V
wave is applied to SMA connector J4 to be used as the DAC sample clock. The signal is converted to a
differential clock by transformer T4 and provides the CLK2 and CLK2C inputs to the DAC5687 device.
This input represents a 50-Ω load to the source. In order to preserve the specified performance of the
DAC5687 converter, the clock source should feature low jitter. Using a clock with a 50% duty cycle gives
optimum dynamic performance.
4.2

Input Data

The DAC5687 EVM can accept 1.8-V or 3.3-V CMOS logic level data inputs through the 34-pin headers
J13 and J14 per Table 2
series dampening resistors to minimize digital ringing and switching noise. Jumper W2 determines which
voltage level is to be used for the logic inputs.
Pin Description
1 CMOS data bit 15 (MSB)
2 GND
3 CMOS data bit 14
4 GND
5 CMOS data bit 13
6 GND
7 CMOS data bit 12
8 GND
9 CMOS data bit 11
10 GND
22 DAC5687 EVM
Table 1. DAC5687 EVM Parts List (continued)
Bill of Material For DAC5687
Qty. Part Number
1 CDCV304PW
1 SN74HC241DW
2 SN74HCT14PWR
2 T4-1-KK8
2 TCM4-1W
1 T1-6T-KK81
1 745536-2
1 EVQ-PJX04M
and Table 3. The board provides options for 50-Ω termination to ground and
Table 2. Input Connector J13 (Data A Bus)
Vendor Ref Des
TI U5
TI U4
TI U2, U3
Mini-circuits T1, T2
Mini-circuits T3, T4
Mini-circuits T5
AMP J1
Panasonic S1
, 0-V offset, 50% duty cycle external
PP
, 0-V offset, 50% duty cycle external square
PP
Pin Description
18 GND
19 CMOS data bit 6
20 GND
21 CMOS data bit 5
22 GND
23 CMOS data bit 4
24 GND
25 CMOS data bit 3
26 GND
27 CMOS data bit 2
SLWU017B – APRIL 2005 – Revised March 2007
www.ti.com
Not Installed
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