Texas Instruments DAC5687 EVM User Manual page 14

DAC5687 EVM Operational Procedure
2.3.2 Configuration Controls
⋅
Full Bypass:
⋅
FIR Bypass:
⋅
FIFO
Bypass:
⋅
FIR A:
⋅
FIR B:
⋅
Dual Clk:
⋅
Interleave:
⋅
Inverse Sinc: Enables inverse sinc filter.
⋅
Half Rate
Input:
⋅
Sif:
⋅
Inv. PLL
Lock:
⋅
PLL Freq:
⋅
PLL Kv:
⋅
Qflag:
⋅
2's Comp:
⋅
Rev A Bus:
⋅
Rev B Bus:
⋅
USB:
⋅
Inv. Clk I(Q):
⋅
Sync_Phstr:
⋅
Sync_cm:
14 DAC5687 EVM
When set, all filtering, QMC, and NCO functions are bypassed.
When set, the interpolation filters are bypassed.
When set to bypass, the internal 4 sample FIFO is disabled. When
cleared, the FIFO is enabled.
A side first FIR filter in highpass mode when set, lowpass mode when
cleared.
B side first FIR filter in highpass mode when set, lowpass mode when
cleared.
Only used when the PLL is disabled. When set, two differential clocks are
used to input the data to the chip; CLK1/CLK1C is used to latch the input
data into the chip, and CLK2/CLK2C is used as the DAC sample clock
When set, interleaved input data mode is enabled; both A and B data
streams are input at the DA(15:0) input pins.
Enables half rate input mode. Input data for the DAC A data path is input
to the chip at half speed using both the DA(15:0) and DB(15:0) input pins.
Sets sif_4pin bit. 4 pin serial interface mode is enabled when on, 3 pin
mode when off. The DAC5687 EVM is configured for a 3 pin serial
interface. The 4 bit serial interface will not work with the DAC5687 EVM.
Only used when PLL is disabled and dual clock mode is disabled. When
cleared, input data is latched into the chip on the rising edge of the
PLLLOCK output pin. When set, input data is latched into the chip on the
falling edge of the PLLLOCK output pin.
Sets PLL VCO center frequency to low or high center frequency.
Sets PLL VCO gain to either high or low gain.
Sets qflag bit. When set, the QFLAG input pin operates as a B sample
indicator when interleaved data is enabled. When cleared, the TXENABLE
rising determines the A/B timing relationship.
When set, input data is interpreted as 2's complement. When cleared,
input data is interpreted as offset binary.
When cleared, Channel A input data MSB to LSB order is DA(15) = MSB
and DA(0) = LSB. When set, Channel A input data MSB to LSB order is
reversed, DA(15) = LSB and DA(0) = MSB.
When cleared, Channel B input data MSB to LSB order is DB(15) = MSB
and DB(0) = LSB. When set, Channel B input data MSB to LSB order is
reversed, DB(15) = LSB and DB(0) = MSB.
When set, the data to DACB is inverted to generate upper side band
output.
Inverts the DAC core sample clock when set, normal when cleared.
When set, the internal clock divider logic is initialized with a PHSTR pin
low to high transition.
When set, the coarse mixer is synchronized with a PHSTR low to high
transition.
SLWU017B – APRIL 2005 – Revised March 2007
Submit Documentation Feedback
www.ti.com