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Circuit Description
Configuration
4:1 Impedance ratio
transformer
Combined Output through
1:1 Impedance ratio
Transformer
4.3.2
Unbuffered Differential Output
To provide unbuffered differential outputs, the EVM must be configured as follows: remove R6-R9, R21,
R22, T1, and T2; install R5 (24.9), R10 (24.9), R19 (24.9), R20 (24.9), R24, R27-R30, and R32. With a 20
mA full-scale output current, this configuration will provide a 0.5 Vpp output.
4.3.3
PLL Lock
With the internal PLL enabled (W3 installed between pins 1 and 2), when the PLL is locked to the CLK1
input, PLLOCK OUT (J2) is driven high. With the internal PLL disabled, the PLLLOCK OUT is an output
clock that can be used by external devices to clock the input data to the DAC5687. This signal is the
CLK2 signal divided down by the interpolation rate and phase-aligned to allow the user to clock data into
the DAC5687 with the required setup and hold times.
4.4
Control Inputs
The DAC5687 device has five discrete inputs to control the operation of the device.
4.4.1
Sleep Mode
The DAC5687 EVM provides a means of placing the DAC5687 device into a power-down mode. This
mode is activated by placing a jumper between pins 5 and 6 on header J15.
4.4.2
Reset
The DAC5687 EVM provides a means of resetting the DAC5687 device. Pressing switch S1 or sending
J15 pin 29 low provides an active low reset signal to the DAC5687 device.
4.4.3
Phase Synchronization
The DAC5687 EVM provides a means to phase synchronize the DAC5687 device. Placing an active high
signal on J15 pin 8 (PHSTR) resets the internal NCO accumulator register.
4.4.4
TxENABLE
TxENABLE must be high to enable the DAC5687 to process data. When low, the DAC5687 device is
forced to a constant dc output at IOUTA and IOUTB. When in the interleaved mode and MEM_QFLAG bit
is set to 0, TxENABLE syncronizes the data of channels A and B. When TxENABLE goes high, data
present at the next clock rising edge is treated as I data. The next valid data is then treated as Q data and
so on. TxENABLE is controlled by J15 pin 11.
4.4.5
QFLAG
QFLAG is an input used to indicate Q sample data during the interleaved mode when the QFLAG
interleave bit (3) is set in register #9, MEM_QFLAG. When QFLAG is high, input data is treated as Q data,
and when low, data is treated as I data. QFLAG is controlled by J15 pin 14.
24
DAC5687 EVM
Table 4. Transformer Output Configuration (continued)
(1)
Components Installed
R5, R10, R19, R20, R23, R26, C60, C61, T1(4:1), T2 (4:1)
R6-R9, R42, C40, T5
Components Not Installed
R6-R9, R21, R22, R24, R27-R33
R5, R10, R19-R22, R27-R33, R41,
T1, T2
SLWU017B – APRIL 2005 – Revised March 2007
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