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Hardware
Figure 6. NOR/NAND Booting vs FPD-Link Video Multiplexing
Table 12. NOR/NAND Booting vs FPD-Link Video Mux Control
Interface
NOR_BOOTn (1),
GPMC_AD and
Low (SW5.P2 = ON)
GPMC_nCS0
High (SW5.P2 = OFF)
VOUT3B
NA
(1) Routing control for GPMC_nCS0 is "shared" between NOR and NAND Flash memories. Ensure that only one DIP switch,
SW5.P1 or SW5.P2, is ever set to "ON" state at any one time so that GMPC_nCS0 is only connected to one memory. Failure to
adhere to this requirement will cause NOR & NAND memory data bus contention.
(2) GPIO Expander (U57) connections to "Board Signal" nets are intended to provide a "read-only" feature to determine boot image
source NOR or NAND). Boot image selection must be set before power on sequence by setting DIP Switches SW2 and SW3
along with SW5.P1 and .P2 appropriately, as shown above.
(3) Bus Logic Switch select input S1 is the inversion of select input S0 connected to SEL_GPMC_AD_VID_S0 net controlled via
GPIO Expander U57.P0.
(4) Bus Logic Switches (RU33, 88 and 94) power-up with S0 = High via pull-up resistor resulting in GPMC_AD bus routed to
memories (S1, S0 = 0, 1).
(5) GPIO Expander (U57) is accessible via I2C1, address 0x21.
3.4.2
QSPI vs NOR Flash Booting
The CPU can be booted from either a QSPI or NOR Flash memory component. The memory interface
signals are routed through a "Resistor Bypass Path" for optimal QSPI signal integrity (SI) or "Bus Logic
Switch Path" for flexible boot image selection. The source and load "muxing resistors" that enable the
"Resistor Bypass Path" have been installed on CPU boards as the default configuration for QSPI booting
with optimal SI. As a consequence, six of the upper GMPC address signals (A13 – A18) are not
connected to the NOR Flash memory due to source muxing resistors being "No-Mount" on the "Bus Logic
Switch Path". This limits the addressable NOR memory to an 8KByte range (A0-A12) due to default mux
resistor mounting. The "resistor muxing" option would need to change to route the GPMC signals via "Bus
Logic Switch Path" to the NOR Flash memory in order to access the full addressable range of the NOR
memory.
16
DRA7x EVM CPU Board
(2)
NAND_BOOTn (1),
(2)
High (SW5.P1 = OFF)
Low (SW5.P1 = ON)
NA
Copyright © 2016, Texas Instruments Incorporated
SEL_GPMC_AD_VID_S0
(3), (4),
(5)
Device
High
NOR Flash
NAND Flash
Low
FPD-Link
SPRUI50 – February 2016
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