Table of Contents
Advertisement
AMI BIOS Utility
DRAM WRITE BURST TIMING
This parameter adjusts the write wait state between L2 and DRAM cache. The
L2 cache is processed through write-back method and each cache write
process consists of four continuous cache write cycles. Therefore, it has four
settings to adjust.
The parameter settings are
X444, X333,
and
X222
. Faster DRAMs
X
require shorter wait states. The value of
depends on the DRAM Lead-off
Timing parameter setting.
FAST RAS TO CAS DELAY
This option specifies the wait state between the row address strobe (RAS) and
3 clocks
column address strobe (CAS) signals. The available settings are
2 clocks
and
.
DRAM LEAD-OFF TIMING
This option specifies the DRAM waiting time or the delay before data can be
accessed. Some DRAMs may require a longer delay to access data. The
11-7-3, 10-6-3, 11-7-4,
10-6-4
selections are
and
.
REFRESH RAS# ASSERTION
This function controls the number of clocks required to assert RAS# for refresh
4 clocks
5 clocks
cycles. The available settings are
and
.
FAST EDO PATH SELECT
Enable this option to select a fast path for CPU to DRAM read cycles to
minimize the lead-off time. This is applicable only for EDO DRAMs. For other
Disabled
DRAM types, we recommend that you set this to
.
3-16
Advertisement
Table of Contents
