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BVP-9500WS (UC) : S/N 10001 and Higher
BVP-9500WS (J)
: S/N 30001 and Higher
BVP-9500WSP (CE) : S/N 40001 and Higher
CN-1928
MB-830
VA-200
R_OHB_VIDEO
R_WHITE_SHADE
OHB
G_OHB_VIDEO
(FEMALE)
-EXTERNAL SIDE-
G_WHITE_SHADE
B_OHB_VIDEO
B_WHITE_SHADE
SER_DATA1
LO_V_BLKG
SER_CLK
VCO CONT
RET_1_R
RET1_TOP
RET2_TOP
RET_LENS
EXTENDER_ON
VTR_LENS
ZEBRA_ON
SPARE
-EXTERNAL SIDE-
UNREG+12V
OUTPUT ENABLE
RE(X)
RE(Y)
VTR SAVE
SWITCH SCAN0-4
SWITCH SCAN2,3
RET1(R)
A/D1
CN-1929
RET1,2 (TOP) ON
SWITCH SCAN2-4
UP TALLY (R),(G)
A/D1,EXTENDER_ON_IN
Overall (2/2)
R GAIN
R
R PRE
R_AD(X)
R_AD(X)
AMP
CONT.
AMP
KNEE
R MOD
L.P.F
SHAD
G GAIN
G
G PRE
G_AD(X)
G_AD(X)
AMP
CONT.
AMP
KNEE
G MOD
L.P.F
SHAD
B GAIN
B
B PRE
B_AD(X)
B_AD(X)
AMP
CONT.
AMP
KNEE
B MOD
L.P.F
SHAD
SYNC
SEP
R_GAIN
G_GAIN
R_FLARE
D/A
ANALOG
B_GAIN
G_FLARE
CONV.
MULTI/
B_FLARE
DEMULTI
VCO CONT
X3/X1
D/A
IIC_SW_SDA
CONV.
IIC_SW_SCL
CN101
LENS
VF
(FEMALE)
(FEMALE)
-EXTERNAL SIDE-
SW-1008
AUTO
VTR
GAIN
OUTPUT
KNEE
WHITE
STBY
CAM
ON
L
B
M
A
H
RPE
SAVE
BARS
OFF
SET
SW-1009
DISPLAY
TESTOUT
ENTER
ON
ENC
SWITCH SCAN
VIR
OFF
RGB
0-4
START
OFF
CANCEL
MENU
SEL
7
SEL
ON
2
SEL
(N.C)
SW-937
SW-936
S1
RET1
RET2
2
2
3
INCOM
FILTER
5
2
4
2
ND
CC
FILTER
LOCAL
SW-1011
Overall (2/2)
AD-157
L.P.F
R_AD_OUT
AMP
12
R A/D
(18MHz)
LATCH
CONV.
12
L.P.F
AMP
(54MHz)
L.P.F
12
G_AD_OUT
AMP
G A/D
(18MHz)
LATCH
CONV.
12
L.P.F
AMP
(54MHz)
L.P.F
12
B_AD_OUT
AMP
B A/D
(18MHz)
LATCH
CONV.
12
L.P.F
AD_CLOCK_GATE
AMP
(54MHz)
CLOCK
BUFFER
AD_CLOCK
SYNC
PHASE
PHASE
SEP.
COMP
LOCKED LOOP
OHB-PLL-H
AT-128
ND POSI
CC POSI
ZOOM POSI
IRIS POSI
FOCUS_POSI
EX.P_POSI
ROTARY ENCODER (X)
ROTARY ENCODER (Y)
SHUTTER
AUTO
W/B BAL
RET1
WHT
CCD TXD
BLK
CCD TRANSMIT
CCD RXD
DATA SIO
SW-1010
DIAG
SWITCH SCAN0-4
2
I
C (OHB) SDA
CN-1930
I
2
C (OHB) SCL
C (SW) SDA
I
2
REMOTE
C (SW) SCL
I
2
AT CLOCK
MONITOR VD
MONITOR SYNC
6-4
6-4
LINE1
SEL-1A-IN
SEL-1A-OUT
36
36
AD_RGB
SDRAM
SEL-1B-IN
SEL-1B-OUT
(1A)
36
36
MEM
SDRAM
CONTROL
(1B)
FPGA
LINE2
SEL-2A-IN
SEL-2A-OUT
32
32
SDRAM
SEL-2B-IN
SEL-2B-OUT
(2A)
32
32
SDRAM
(2B)
LINE3
SEL-3A-IN
SEL-3A-OUT
32
32
SDRAM
SEL-3B-IN
SEL-3B-OUT
(3A)
32
32
SDRAM
(3B)
AD-PLL-H
L1-OUT/L2-OUT/L3-OUT
7
L1/L2/L3 SDRAM
6
L1-OUT2 CLK
54/18 CLK (X)
INV.
FPGA CLK
X3/X1
C (IC3) _SDA
I
2
I
2
C (IC2) _SDA
C (IC1) _SDA
I
2
DRIVER/
RECEIVER
REMOTE TVD
CPU
RM DATA
REMOTE RVD
INTERFACE
CHU DATA
CHU/CCU
CCU DATA
INTERFACE
CLOCK
SER DATA0
GEN.
SER DATA1
18M
SERIAL
INTERFACE
NVSRAM
FLASH
IRIS CONT
SRAM
D/A
EEPROM
MEMORY
LENS_DATA
LENS DATA
LENS_DATA
SIO
IRIS AUTO/MANU
CHARACTER
5
CHARACTOR
CHARACTER BACK
I/O
/TITLE
GEN.
PORT
TITLE BACK
ABNORMAL IND
(SHRINKER LENS ON)
SWITCH SCAN0-4
6M
5
UP TALLY (G),(R)
9M
CLOCK
12M
GEN.
18M
MEM-98
DA-143
(1/2)
LATCH
CONFIG RST
FPGA RST
SDRAM RST
525/625
X3/X1
LATCH
LATCH
AD-PLL-H
X3/X1
SER_CLK
LD_V_BLK
LD_OHB
TITLE
BVP-9500WS/9500WSP MM
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