Nvidia Jetson Nano Product Design Manual page 5

Figure 2-1. Jetson Nano Block Diagram..........................................................................5
Figure 4-1. Jetson Nano Module Installed in SODIMM Connector ................................... 10
Figure 4-2. Module to Connector Assembly Diagram ..................................................... 10
Figure 5-1. Jetson Nano Power and Control Block Diagram........................................... 12
Figure 5-2. System Power and Control Block Diagram .................................................. 13
Figure 5-3. Power Up Sequence.................................................................................... 13
Figure 5-4. Power Down - Initiated by SHUTDOWN_REQ* Assertion) ............................. 13
Figure 5-5. Power Down - Sudden Power Loss.............................................................. 14
Figure 6-1. USB Connection Example............................................................................ 17
Figure 6-2. IL/NEXT Plot ............................................................................................... 20
Figure 6-3. Trace Spacing for TX/RX Non-Interleaving ................................................... 20
Figure 6-4. Via Structures............................................................................................. 20
Figure 6-5. ESD Layout Recommendations.................................................................... 21
Figure 6-6. Component Order ....................................................................................... 21
Figure 6-7. Example PCIe Connections ......................................................................... 23
Figure 6-8. AC Cap Voiding ........................................................................................... 25
Figure 6-9. Jetson Nano Ethernet Connections ............................................................. 26
Figure 6-10. Gigabit Ethernet Magnetics and RJ45 Connections....................................... 27
Figure 7-1. DSI 1 x 2 Lane Connection Example ............................................................. 29
Figure 7-2. DP/eDP Connection Example on DP0 Pins ................................................... 32
Figure 7-3. eDP Differential Main Link Topology ............................................................ 33
Figure 7-4. S-parameter............................................................................................... 35
Figure 7-5. Via Topology #1 .......................................................................................... 35
Figure 7-6. Via Topology #2 .......................................................................................... 35
Figure 7-7. HDMI Connection Example.......................................................................... 37
Figure 7-8. HDMI Clk and Data Topology ....................................................................... 38
Figure 7-9. IL and FEXT Plot ......................................................................................... 41
Figure 7-10. TDR Plot..................................................................................................... 41
Figure 7-11. HDMI Via Topology ...................................................................................... 41
Figure 7-12. Add-on Components - Top .......................................................................... 41
Figure 7-13. Add-on Components - Bottom .................................................................... 42
Figure 7-14. AC Cap Void ................................................................................................ 42
Figure 7-15. RPD, Choke, FET Placement ....................................................................... 42
Figure 7-16. ESD Footprint ............................................................................................. 42
Figure 7-17. ESD Void..................................................................................................... 42
Figure 7-18. SMT Pad Trace Entering.............................................................................. 43
Figure 7-19. SMT Pad Trace Between ............................................................................. 43
NVIDIA Jetso n Nano
List of Figures
DG-09502-001_v2.1 | v