Nvidia Jetson Nano Product Design Manual page 47

Parameter
Reference plane
Trace spacing/Length/Skew
Trace loss characteristic:
Trace spacing (pair-pair)
Microstrip: pre 1.4b
Microstrip: 1.4b/2.0
Trace spacing
(Main link to DDC) Microstrip
Max total length/delay (1.4b/2.0 - up to
5.94Gbps)
Microstrip (5x spacing)
Microstrip (7x spacing)
Max Total Length/Delay (Pre-1.4b)
(up to 165Mhz) Microstrip
Max intra-pair (within pair) skew
Max inter-pair (pair to pair) skew
Max GND transition via distance
Via
Topology
Minimum impedance dip
Recommended via dimension
GND via
Max # of vias
Max via stub length
Topology
The main route via dimensions should comply with the via structure rules (See via section)
For the connector pin vias, follow the rules for the connector pin vias (See via section)
The traces after main route via should be routed as 100Ω differential or as uncoupled 50ohm SE traces on
PCB top or bottom.
Max distance from R to main trace (seg B)
PD
Max distance from AC cap to RPD stubbing
point (seg A)
Max distance between ESD and signal via
Add-on Components
Example of a case where space is limited for
placing components.
AC Cap
NVIDIA Jetso n Nano
Requirement
GND
< 0.8
< 0.4
Stripline 3x
4x
5x to 7x
Stripline 3x
5x
Stripline
63.5/2.5 (437)
50.8/2.0 (300)
63.5/2.5 (375)
254/10 (1500)
Stripline
225/8.5 (1500)
0.15 (1)
150
1x
Y-pattern is recommended
keep symmetry
97
92
drill/pad 200/400
Antipad 840
via pitch 880
Place GND via as symmetrically as possible to data pair
vias. Up to four signal vias (2 diff pairs) can share a single
GND return via
PTH via 4 if all vias are PTH via
u-via Not limited if total channel loss meets IL spec.
0.4
1
~0
3
Top: See Figure 7-12
Units Notes
The max length is derived based on this
dB/in. @ 3GHz
characteristic. See Note 1.
dB/in. @ 1.5GHz
For Stripline, this is 3x of the thinner of above and
below.
dielectric
dielectric For Stripline, this is 3x of the thinner of above and
below.
Propagation delay: 175ps/in. for stripline, 150ps/in.
for microstrip).
mm/in (ps)
mm/in (ps) Propagation delay: 175ps/in. for stripline, 150ps/in.
for microstrip).
mm (ps) See notes 1, 2, and 3
ps See notes 1, 2, and 3
For signals switching reference layers, add one or
Diff pair via pitch
two ground stitching vias. It is recommended they
be symmetrical to signal vias.
Xtalk suppression is the best by Y-pattern. Also, it
can reduce the limit of pair-pair distance. Need
review (NEXT/FEXT check) if via placement is not Y-
Ω@200ps
pattern. See Figure 7-11
Ω@35ps
uM
GND via is used to maintain return path, while its
Xtalk suppression is limited
mm long via stub requires review (IL and resonance dip
check)
See Figure 7-8
mm
mm
mm
Bottom: See Figure 7-13
Display
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