Nvidia Jetson Nano Product Design Manual page 2

DG-09502-001_v2.1
Version Date
1.0 June 7, 2019
2.0 March 2, 2020
2.1 July 1, 2020
NVIDIA Jetso n Nano
Document History
Description of Change
Initial Release
•
Added MPIO pad code and POR columns to the pin description
tables through the design guide
•
Added chapter on modular connector (Chapter 3)
•
Updated power down figures (Figure 4-4 and Figure 4-5)
•
Updated Figure 5-1 to show details of FET used as level shifter
for VBUS Detect to show it is inverted.
•
Corrected USB2 module pin numbers in Figure 5-1
•
Corrected PCIE0_TX3/RX0 pin numbers in Figure 5-7
•
Updated the notes to the PCIe signal routing requirements
table (Table 5-9)
•
Updated Gigabit Ethernet controller in Section 5.3
•
Updated Figure 7-1 to "4 Lanes..."
•
Added Chapter 3 "Developer Kit Feature Considerations"
•
Updated notes for all pin description tables
•
Corrected module pin numbers in Figure 7-2
•
Updated Table 9-1 include both 1.8V and 3.3V pins, since the
pins are associated with a rail that may be set to one or the
other voltage
•
Updated Figure 9-1 to change SDMMC_SD to connect to
generic GPIO
•
Removed GPIO08 for SD Card Detect from Table 9-3 since
figure shows generic GPIO
•
Updated Table 11-6 to mention buffer on module
•
The Jetson Nano pin description and design checklist are now
attachments to this design guide
DG-09502-001_v2.1 | ii