Figure 11-2. Spi Connections; Figure 11-3. Basic Spi Master And Slave Connections - Nvidia Jetson Nano Product Design Manual

Pin # Module Pin Name Tegra X1 Signal
110 SPI1_CS0* SPI2_CS0
112 SPI1_CS1* SPI2_CS1
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The directions for SPI[1:0]x are true when used for those functions. Otherwise as GPIOs, the directions are bidirectional.
3. The MPIO Pad Codes are described in the
(PinMux)" section for details.
4. The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
software. "z" is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.

Figure 11-2. SPI Connections

Tegra – SPI
SPI
AUDIO_HV
Figure 11-3 shows the basic connections used.

Figure 11-3. Basic SPI Master and Slave Connections

Jetson Master
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
NVIDIA Jetso n Nano
Usage/Description
SPI 1 Chip Select 0
SPI 1 Chip Select 1
Tegra X1 SoC Technical Reference Manual
Jetson
SPI1_SCK
SPI1_MISO
SPI1_MOSI
SPI1_CS0
SPI1_CS1
SPI2_SCK
SPI2_MISO
SPI2_MOSI
SPI2_CS0
SPI2_CS1
SPI Slave Device
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
Usage on NVIDIA DevKit
Carrier Board
"Multi-Purpose I/O Pins and Pin Multiplexing
SPI0_SCK
91
SPI0_MISO
93
SPI0_MOSI
89
SPI0_CS0*
95
SPI0_CS1*
Routed to 40-pin
97
Expansion Header on
SPI1_SCK
DevKit carrier board
106
SPI_MISO
108
SPI1_MOSI
104
SPI1_CS0*
110
SPI1_CS1*
112
Jetson Slave
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
Miscellaneous Interfaces
MPIO Pad
Direction Pin Type
Code
CZ
CZ
SPI Master Device
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
DG-09502-001_v2.1 | 60
Power-on
Reset
pu
pu