Nvidia Jetson Nano Product Design Manual page 48

Parameter
Value
Max via distance from BGA
Location
Placement PTH design
Micro-via design
Void
Pull-down Resistor (R ), choke/FET
PD
Value
Location.
Layer of placement
Choke between R and FET
PD
Max trace Rdc
Max trace length
Void
Common-mode Choke (Not recommended – only used if absolutely required for EMI issues)
See Appendix A for details on CMC if implemented.
ESD (On-chip protection diode can withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option)
Max junction capacitance
(IO to GND)
Footprint
Location
Void
Series Resistor (R ) – Series resistor on N/P path for HDMI 2.0 (mandatory)
S
Value
Location
Void
Trace at Component Region
Value
Location
Trace entering the SMT pad
Trace between components
HDMI connector
Connector voiding
General: See Chapter 15 for guidelines related to Serpentine routing, routing over voids and noise coupling
Notes:
1. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be
reduced.
2. The average of the differential signals is used for length matching.
3. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or any discontinuity to minimize
common mode conversion
4. If routing includes a flex or 2nd PCB, the max trace delay and skew calculations must include all the PCBs/flex routing. Solutions with flex/2nd PCB may
not achieve maximum frequency operation.
NVIDIA Jetso n Nano
Requirement
0.1
7.62 (52.5)
must be placed before pull-down resistor
Place cap on bottom layer if main-route above core
Place cap on top layer if main-route below core
Not Restricted
GND (or PWR) void under/above the cap is needed. Void
size = SMT area + 1x dielectric height keepout distance
500
Must be placed after AC cap
Same layer as AC cap. The FET and choke can be placed
on the opposite layer thru a PTH via
choke 600 or
1
≤20
4
GND/PWR void under/above cap is preferred
0.35
Pad right on the net instead of trace stub
After pull-down resistor/CMC and before R
GND/PWR void under/above the cap is needed. Void size =
1mm x 2mm for 1 pair
≤ 6
After all components and before HDMI connector
GND/PWR void under/above the R
distance.
100
At component region (Microstrip)
One 45°
Uncoupled structure
Voiding the ground below the signal lanes 0.1448(5.7mil)
larger than the pin itself
Units Notes
uF
mm (ps)
The distance between the AC cap and the HDMI
connector is not restricted.
See Figure 7-14
Ω
Placement: See Figure 7-15
Ω @ 100 MHz Can be choke or Trace. Recommended option for
HDMI2.0 HF1-9 improvement.
uH@DC-100 MHz
mΩ
mm
pF e.g. Texas Instruments TPD4E02B04DQAR
See Figure 7-16
S
See Figure 7-17
Ω ± 10%. 0ohm is acceptable if the design passes the
HDMI2.0 HF1-9 test. Otherwise, adjust the R
to ensure the HDMI2.0 tests pass: Eye diagram,
Vlow test and HF1-9 TDR test
device is needed. Void size = SMT area + 1x dielectric height keepout
S
Ω ± 10%
See Figure 7-18
See Figure 7-19
See Figure 7-20
Display
value
S
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