Nvidia Jetson Nano Product Design Manual page 27

Parameter
If routing on the same layer, strongly recommend not interleaving TX and RX lanes
If it is necessary to have interleaved routing in breakout, all the inter-pair spacing should follow the rule of inter-SNEXT
The breakout trace width is suggested to be the minimum to increase inter-pair spacing
Do not perform serpentine routing for intra-pair skew compensation in the breakout region
See Figure 6-3
Min inter-S
NEXT
(between TX/RX)
Min inter-S
FEXT
(between TX/TX or RX/RX)
Max length
Trace Spacing
Pair-Pair (inter-pair)
To plane and capacitor pad
To unrelated high-speed signals Microstrip / Stripline
Trace Length/Skew
Trace loss characteristic @ 2.5GHz
Breakout region
Max trace length/delay
Max PCB via distance/delay from pin
Max within pair (intra-pair) skew
Differential pair uncoupled length/delay
AC Cap
Value
Location (max distance to adjacent discontinuities)
Via
via structure
GND via
AC cap pad voiding
Max via stub length
ESD
Preferred device
Max junction capacitance (IO to GND)
Location (max distance to connector)
Layout recommendations
Common-mode choke (not recommended – only used if absolutely required for EMI issues)
See Chapter 15 for details on CMC if implemented.
Component Order
Component order
NVIDIA Jetso n Nano
Requirement
Breakout 4.85x
Main-route 3x
Breakout 1x
Main-route 1x
Breakout 11
Main-route Max trace length
- LBRK
Microstrip / Stripline 4x / 3x
Microstrip / Stripline 4x / 3x
4x / 3x
< 0.7
Max trace delay 11
152.3 (1014)
6.29 (41.9)
0.15 (1)
6.29 (41.9)
0.1
8 (53.22)
Y-pattern is strongly
recommended (keep symmetry)
Place GND via as symmetrically
as possible to the data pair vias.
Up to 4 signal vias (2 diff pairs)
can share a single GND return
via"
GND (or PWR) void under / above
the cap is preferred
0.4
0.8
8 (53)
Units Notes
Dielectric This is the recommended dimension for meeting NEXT
height requirement
Stripline structure in a GSSG structure is assumed; it
Inter-pair
holds in broadside-coupled stripline structure
spacing
All values are in terms of minimum dielectric height
mm
dielectric
The following max length is derived based on this
dB/in
characteristic. See Note 1.
mm Minimum width and spacing
mm (ps)
mm (ps)
mm (ps)
mm (ps)
uF Smallest size preferred (i.e. 0201). See note under USB
Connection Diagrams for details on when AC capacitors
are required
The AC cap location should be located as close as possible
mm (ps)
to nearby discontinuities
Xtalk suppression is best when using Y-pattern. Can also
reduce the limit of pair-pair distance. See Figure 6-4.
GND via is used to maintain return path, while its Xtalk
suppression is limited.
Voiding is required if cap size is 0603 or large.
mm long via stub requires review (IL and resonance dip check).
Type: Texas Instruments TPD4I05U06. Optional. Place ESD
component near connector
pF
mm (ps)
See USB 3.0 Guideline Figure 6-5
Chip ̶ AC capacitor (TX only) ̶ common mode choke ̶
ESD ̶ Connector: See Figure 6-6.
USB and PCI Express
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