Agilent Technologies 54830 Series Service Manual page 163

Chapter 8: Theory of Operation
Block-Level Theory
Figure 8-2
Upper
Lower
Upper
Lower
Scope Front Panel
Acquisition Block Diagram
8–6
ADC
8 Bit
CLK
Zeum
8 Bit
CLK
Deceleration &
4GSa ADC Processing
LSI Logic ASIC
8 Bit
Deceleration &
Processing
CLK
LSI Logic ASIC
8 Bit
CLK
Reference Clock
Generation
Coarse Gate
Interpolator
Fine Gate
Sys
Trig
DACS
High Speed Trigger Circuitry
Trig 2
Trig 1
Clock Data
Delay Delay
Circuit Circuit
500
MHz
Comp.
Scope Back Panel
Acquistion Memory
Addr
PHI1
32 Bit
PHI2 Addr
Acquisition
PHI1
Data
Memory
32 Bit
32 Bit
8 8Mbit
PHI3
SGRAMs
Acquisition
PHI2
32 Bit
Data
Memory
32 Bit
PHI4
8 8Mbit
PHI3
32 Bit
SGRAMs
32 Bit
PHI4
32 Bit
Clock
Data
Hold Off
ATrig
CH 4
CH 3
CH 2
CH 1
TrigOut
Calibrat
or,
Probe
Comp
& Trig
Out
CH 1 & 2
Digital 0-15
Secondary PCI Bus
PCI
FPGA
Bridge
Primary PCI Bus
Ribbon
Cable
INTERFACE
CARD
54830b10