Appendix C: Xilinx Constraints File - Xilinx VC707 User Manual

Xilinx Constraints File
The VC707 board Xilinx design constraints (XDC) file template provides for designs targeting the
VC707 board. Net names in the constraints correlate with net names on the latest VC707 board
schematic. Users must identify the appropriate pins and replace the net names listed here with net
names in the user RTL. See Vivado Design Suite User Guide Using Constraints (UG903)
[Ref
The FMC connectors J35 and J37 are connected to 1.8V V
implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by
each customer.
Refer to the Virtex-7 FPGA VC707 Evaluation Kit product page (www.xilinx.com/vc707), Docs &
Designs tab, for the latest versions of the FPGA xdc constraint file.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
12]for more information.
www.xilinx.com
Appendix C
banks. Because each user's FMC card
cco
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