Pci Express Edge Connector - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features
Table 1-10:
Transceiver Bank
For more information on the GTX transceivers see UG476, 7 Series FPGAs GTX Transceivers
User Guide.

PCI Express Edge Connector

[Figure
The 8-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive
signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as
a 100Ω differential pair. The 7 series FPGAs GTX transceivers are used for multi-gigabit per
second serial interfaces.
The XC7K325T-2FFG900C FPGA (-2 speed grade) included with the KC705 board supports
up to Gen2 x8.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK1 pins of Quad 115. PCIE_CLK_Q0_P is connected to FPGA U1 pin U8, and
the _N net is connected to pin U7. The PCI Express clock circuit is shown in
30
GTX Interface Connections for FPGA U1 (Cont'd)
Associated Net Name
MGT_BANK_116 GTXE2_CHANNEL_X0Y4
GTXE2_CHANNEL_X0Y5
GTXE2_CHANNEL_X0Y6
GTXE2_CHANNEL_X0Y7
MGTREFCLK0
MGTREFCLK1
MGT_BANK_117 GTXE2_CHANNEL_X0Y8
GTXE2_CHANNEL_X0Y9
GTXE2_CHANNEL_X0Y10
GTXE2_CHANNEL_X0Y11
MGTREFCLK0
MGTREFCLK1
MGT_BANK_118 GTXE2_CHANNEL_X0Y12
GTXE2_CHANNEL_X0Y13
GTXE2_CHANNEL_X0Y14
GTXE2_CHANNEL_X0Y15
MGTREFCLK0
MGTREFCLK1
1-2, callout 13]
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Connections
PCIe3
PCIe2
PCIe1
PCIe0
Si5324
FMC LPC GBT_CLK0
SMA
SGMII
SFP+
FMC LPC DP0
SGMII_CLK
SMA_CLK
FMC HPC DP0
FMC HPC DP1
FMC HPC DP2
FMC HPC DP3
FMC HPC GBT_CLK0
FMC HPC GBT_CLK1
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013
Figure 1-15.