Attach The Gtx Quad Connector - Xilinx Virtex-7 FPGA VC7203 Getting Started Manual

X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the GTX transceiver reference
clocks in the IBERT demonstrations.
SMA connectors on the clock module which can be connected to the reference clock cables.
Note:
board.
X-Ref Target - Figure 1-3
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note:
SuperClock-2 module.
For the GTX IBERT demonstration, the output clock frequencies are preset to 156.25 MHz.
For more information regarding the SuperClock-2 module, see HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770).

Attach the GTX Quad Connector

Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
A
GTX Connector Pad
Figure 1-2: A – GTX Connector Pad. B – GTX Connector Pinout
The image in Figure 1-3
SI570_CLK_P CLKOUT1_P
SI570_CLK_N CLKOUT1_N
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
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Running the GTX IBERT Demonstration
B
Figure 1-3 shows the locations of the differential clock
is for reference only and might not reflect the current revision of the
CLKOUT2_P
CLKOUT2_N
GTX
P
N
P N
N P
P N
P
N
P N
P
N
P N
P
N
P N
GTX Connector Pinout
UG847_c1_02_110112
CLKOUT3_P CLKOUT4_P
CLKOUT3_N CLKOUT4_N
UG847_c1_03_103112
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