Memory Access Controller; Figure 2 Erac Interconnection - HP 9000 V-Class Operator's Manual

Overview
The node
Figure 2 ERAC interconnection
EPAC EPAC EPAC EPAC EPAC EPAC EPAC EPAC
ERAC ERAC ERAC ERAC
EMAC EMAC EMAC EMAC EMAC EMAC EMAC
EMAC

Memory access controller

The EMAC controls all accesses to memory. Each EMAC controls four
banks of memory, allowing up to 32 banks in an eight-EMAC node.
Memory banks consist of Single Inline Memory Modules (SIMMs) of
Synchronous Dynamic Random Access Memory (SDRAM).
The EMAC has the following buses:
ERAC Port (A, B)—Four unidirectional, 32-bit interfaces, two in each
direction. This interface supports a total simultaneous read-write
bandwidth of 1.9 Gbytes/sec.
Even Memory—Bidirectional, 88-bit interface to the even memory banks
associated with the EMAC.
Odd Memory—Bidirectional, 88-bit interface to the odd memory banks
associated with the EMAC.
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