Utilities Board And Core Logic Bus - HP 9000 V-Class Operator's Manual

Overview
The node
A processor accesses memory by sending a request, in the form of
packets, to an ERAC. The request is then forwarded to one of the
EMACs. The EMAC routes requests into even and odd pending queues.
Some packets not destined for memory are routed from processor to
processor through the EMAC. These packets are routed directly to the
output ports.
The EMAC accesses one of four available memory banks, checking the
Error Correction Code (ECC). Provided no additional coherency
operations are required, the data accessed from memory is returned to
the processor by sending a response back to the ERAC, which forwards
the response to the EPAC.

Utilities board and core logic bus

The ECUB, or Utilities board, connects to the core logic bus and contains
two field-programmable gate arrays (FPGAs): the EPUC and EMUC.
The EPUC allows processors access to the system core logic and booting
firmware, and the EMUC processes the environmental state of the node
and interrupts the processors when appropriate. V-Class servers use the
core logic bus primarily to boot the system and to issue node-local
environmental interrupts.
The core logic bus is a low-bandwidth, multidrop bus that connects each
processor to the control and interface logic (both RS232 and ethernet). A
processor can write to control and status registers (CSRs) accessed using
the core logic bus to initialize and configure the ERAC chips and Utilities
board logic.
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