Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh); Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh); Receive Channel N Flow Control Threshold Register (Rxnflowthresh); Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers

5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in
and described in
Figure 66. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
31
15
Reserved
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Bit Field
31-8 Reserved
7-0 RXFILTERTHRESH

5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)

The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in
described in Table
Figure 67. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
31
15
Reserved
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
Bit Field
31-8 Reserved
7-0 RXnFLOWTHRESH
108 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Table 65.
R-0
Field Descriptions
Value Description
0 Reserved
0-FFh Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
low priority incoming frames. This field should remain 0, if no filtering is desired.
66.
R-0
Field Descriptions
Value Description
0 Reserved
0-FFh Receive flow threshold. These bits contain the threshold value for issuing flow control on
incoming frames for channel n (when enabled).
Reserved
R-0
8 7
RXFILTERTHRESH
Reserved
R-0
8 7
RXnFLOWTHRESH
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Figure 66
R/W-0
Figure 67
R/W-0
SPRUEQ6 – December 2007
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16
0
and
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