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Architecture
2.16 Interrupt Support
2.16.1
EMAC Module Interrupt Events and Requests
The EMAC module generates the following interrupt events:
RXTHRESHOLDPENDn: Receive threshold interrupt for receive channels 0 through 7
RXPENDn: Receive packet completion interrupt for receive channels 0 through 7
TXPENDn: Transmit packet completion interrupt for transmit channels 0 through 7
STATPEND: Statistics interrupt
HOSTPEND: Host error interrupt
USERINT: MDIO user Interrupt
LINKINT: MDIO link Interrupt
As shown in
Figure
the CPU.
EMAC core
MDIO core
2.16.1.1
Receive Threshold Interrupts
Each of the eight receive channels have a corresponding receive threshold interrupt
(RX_THRESH_PEND[0:7]). The receive threshold interrupts are level interrupts that remain asserted
until the triggering condition is cleared by the host. Each of the eight threshold interrupts may be
individually enabled by setting the corresponding bit in the receive interrupt mask set register
(RXINTMASKSET) to 1. Each of the eight channel interrupts may be individually disabled by clearing
the corresponding bit in the receive interrupt mask clear register (RXINTMASKCLEAR) to 0. The raw
and masked receive interrupt status may be read from the receive interrupt status (unmasked) register
(RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED),
respectively. An RX_THRES_PEND[7:0] interrupt bit is asserted when enabled and when the channel's
associated receive channel n free buffer count register (RXnFREEBUFFER) is less than or equal to the
channel's associated receive channel n flow control threshold register (RXnFLOWTHRESH). The
receive threshold interrupts use the same free buffer count and threshold logic as does flow control, but
the interrupts are independently enabled from flow control. The threshold interrupts are intended to give
the host an indication that resources are running low for a particular channel(s).
56
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
12, the EMAC and MDIO interrupts are multiplexed on four interrupts lines going to
Figure 12. EMAC Control Module Interrupt Logic Diagram
Interrupt control and pacing logic
RXTHRESHOLDPEND(0..7)
RXPEND(0..7)
TXPEND(0..7)
STATPEND
HOSTPEND
MDIO_USER
MDIO_LINKINT
Receive threshold interrupt
Receive interrupt
Transmit interrupt
Miscellaneous interrupt
SPRUEQ6 – December 2007
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