Texas Instruments TMS320DM646x User Manual page 5

5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)
5.37 MAC Hash Address Register 1 (MACHASH1)
5.38 MAC Hash Address Register 2 (MACHASH2)
5.39 Back Off Test Register (BOFFTEST)
5.40 Transmit Pacing Algorithm Test Register (TPACETEST)
5.41 Receive Pause Timer Register (RXPAUSE)
5.42 Transmit Pause Timer Register (TXPAUSE)
5.43 MAC Address Low Bytes Register (MACADDRLO)
5.44 MAC Address High Bytes Register (MACADDRHI)
5.45 MAC Index Register (MACINDEX)
5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
5.50 Network Statistics Registers
Appendix A Glossary
SPRUEQ6 - December 2007
Submit Documentation Feedback
.......................................................................
.........................................................................
.................................................................................
......................................................................................................
.......................................
............................................................
............................................................
...............................................
..............................................................
..............................................................
......................................................
......................................................
...........................................
...........................................
116
117
117
118
118
119
119
120
121
121
............................
122
............................
122
123
123
124
133
Contents 5